C
ASIC Design Hardware Engineer - SDC/STA - San Jose, CA (Hybrid)
Accepting applicationsCAONE · San Jose, CA
Contract Entry ASICDFTPerlRTLSynopsys
Posted
3d ago
Category
Design
Experience
Entry
Country
United States
ASIC Design Hardware Engineer - SDC/STA (Hybrid)
Location: San Jose, California, United States of America
You are a diligent Design / SDC Engineer with strong analytical skills and a deep
understanding of timing constraints, including clock groups, exceptions, and clock
exclusivity. Proficient in industry-standard SDC/STA tools and scripting for automation, you
excel at identifying and resolving timing issues across all design levels. You will develop
timing constrains at both block level and full-chip and validate them using industry standard
timing constraints verification tools such as TCM, Time vision. You will collaborate with
Front-end and Back-end teams to understand chip architecture and guide them in refining
design and timing constraints for seamless physical design closure. As part of this team,
you’ll contribute to developing next-generation networking chips.
• Being a member of design team who develops block level and full-chip SDCs and
works with physical design and DFT teams to close full-chip timing in multiple
timing modes.
• You will work design and architecture teams in understanding clocking structure,
develop timing constraints and validate them though constraints verification tool
before releasing them for physical design.
• Option to also do block level RTL design or block or top-level IP integration.
• Helping develop efficient methodology to promote block level SDCs to full-chip, and
to push down full-chip SDCs to block level.
• Helping develop and apply methodology to ensure correctness and quality of SDCs
as early as possible in design cycle.
• Reviewing block level SDCs and clocking diagrams and collaborate with RTL design
owners on SDC development.
• Contribute to full-chip clocking design including diagrams and related
documentation.
Minimum Qualifications
• Bachelor’s Degree in Electrical or Computer Engineering with 6+ years of ASIC or
related experience or Master’s Degree in Electrical or Computer Engineering with 3+
years of ASIC or related experience.
• Experience with synthesis tools (eg. Synopsys DC/DCG/FC), STA tools such as
Primetime and must have knowledge of HDL such as Verilog/SystemVerilog
programming, and scripting languages such as Shell, Perl, and must have strong
experience scripting with TCL.
• Experience with digital design concepts (eg. clocking, timing exceptions and async
boundaries).
• Experience with block/full chip SDC development in functional and test modes.
• Experience with microarchitecture and RTL implementation.
Preferred Qualifications
• Effective documentation, problem-solving, and technical communication skills.
• Experience working cross-functionally and collaborating with various technical
teams.
• You are a problem solver who loves to tackle new challenges and a self-starter who
is highly motivated and thrives on innovative technology.
• You are a strong communicator in a team setting, enjoy working in a dynamic team
environment, and are an out-of-the-box thinker.
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Location: San Jose, California, United States of America
You are a diligent Design / SDC Engineer with strong analytical skills and a deep
understanding of timing constraints, including clock groups, exceptions, and clock
exclusivity. Proficient in industry-standard SDC/STA tools and scripting for automation, you
excel at identifying and resolving timing issues across all design levels. You will develop
timing constrains at both block level and full-chip and validate them using industry standard
timing constraints verification tools such as TCM, Time vision. You will collaborate with
Front-end and Back-end teams to understand chip architecture and guide them in refining
design and timing constraints for seamless physical design closure. As part of this team,
you’ll contribute to developing next-generation networking chips.
• Being a member of design team who develops block level and full-chip SDCs and
works with physical design and DFT teams to close full-chip timing in multiple
timing modes.
• You will work design and architecture teams in understanding clocking structure,
develop timing constraints and validate them though constraints verification tool
before releasing them for physical design.
• Option to also do block level RTL design or block or top-level IP integration.
• Helping develop efficient methodology to promote block level SDCs to full-chip, and
to push down full-chip SDCs to block level.
• Helping develop and apply methodology to ensure correctness and quality of SDCs
as early as possible in design cycle.
• Reviewing block level SDCs and clocking diagrams and collaborate with RTL design
owners on SDC development.
• Contribute to full-chip clocking design including diagrams and related
documentation.
Minimum Qualifications
• Bachelor’s Degree in Electrical or Computer Engineering with 6+ years of ASIC or
related experience or Master’s Degree in Electrical or Computer Engineering with 3+
years of ASIC or related experience.
• Experience with synthesis tools (eg. Synopsys DC/DCG/FC), STA tools such as
Primetime and must have knowledge of HDL such as Verilog/SystemVerilog
programming, and scripting languages such as Shell, Perl, and must have strong
experience scripting with TCL.
• Experience with digital design concepts (eg. clocking, timing exceptions and async
boundaries).
• Experience with block/full chip SDC development in functional and test modes.
• Experience with microarchitecture and RTL implementation.
Preferred Qualifications
• Effective documentation, problem-solving, and technical communication skills.
• Experience working cross-functionally and collaborating with various technical
teams.
• You are a problem solver who loves to tackle new challenges and a self-starter who
is highly motivated and thrives on innovative technology.
• You are a strong communicator in a team setting, enjoy working in a dynamic team
environment, and are an out-of-the-box thinker.
Show more Show less