ASIC Design Engineer

Micro-architecture & RTL Design: Translate functional specifications into detailed micro-architecture and implement high-performance designs using Verilog/SystemVerilog while meeting power and area targets.
Design Verification: Develop functional coverage and SVA assertions to identify corner-case bugs and collaborate closely with the Verification team to ensure robust block validation.
Timing & Physical Design: Partner with the Physical Design team on floorplanning and timing closure, proactively identifying and resolving RTL timing issues to meet frequency targets.
Technical Leadership & Mentoring: Drive design excellence while mentoring and guiding new college graduates and interns, with opportunities to develop technical and leadership skills

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