DS
Analog Layout Engineers
Accepting applicationsDigicomm Semiconductor · Bengaluru, Karnataka, India
Full-Time Entry AnalogCMOSFinFETMixed SignalSERDES
Estimated market salary
₹19-33 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
20h ago
Category
Design
Experience
Entry
Country
India
Exciting Opportunity for Analog Layout Engineers ! Elevate your career with Digicomm Semiconductor Private Limited and take the next leap in your professional journey. Join us for unparalleled growth and development.
Responsibilities:-
Excellent work experience in Analog / Mixed Signal Layout design in advanced FinFET processes like 16nm, 12nm, 10nm, 7nm, 5nm, 3nm
Expertise on complete PNR flow CTS,routing, Timing Closure.
Hands on experience in any or multiple critical blocks such as SERDES, PHY, HDMI, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc.
Excellent understanding of CMOS / Bi-CMOS / SOI / FinFET process
Excellent understanding of CMOS / Bi-CMOS / SOI / FinFET process
Experience in AMS IP integration in full chip according to the guidelines demanded by the Full Chip needs
Excellent problem-solving skills in Routing Congestion, Physical Verification in Custom Layout
Qualifications:- BTECH/MTECH
Experience:- The Engineers with 2 to 8 years of Experience
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Responsibilities:-
Excellent work experience in Analog / Mixed Signal Layout design in advanced FinFET processes like 16nm, 12nm, 10nm, 7nm, 5nm, 3nm
Expertise on complete PNR flow CTS,routing, Timing Closure.
Hands on experience in any or multiple critical blocks such as SERDES, PHY, HDMI, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc.
Excellent understanding of CMOS / Bi-CMOS / SOI / FinFET process
Excellent understanding of CMOS / Bi-CMOS / SOI / FinFET process
Experience in AMS IP integration in full chip according to the guidelines demanded by the Full Chip needs
Excellent problem-solving skills in Routing Congestion, Physical Verification in Custom Layout
Qualifications:- BTECH/MTECH
Experience:- The Engineers with 2 to 8 years of Experience
Show more Show less