NT
VLSI Layout Design Engineer
Accepting applicationsNextiCron Technologies · Bengaluru, Karnataka, India
Full-Time Entry CMOSCadenceVLSIanalog
Estimated market salary
₹19-33 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
21h ago
Category
Design
Experience
Entry
Country
India
#Hiring: VLSI Layout Design Engineer
NextiCron Technologies is expanding its custom IC layout team. We are looking for a VLSI Layout Design Engineer with at least four years of experience in custom IC layout. Strong expertise in physical layout design and a good understanding of semiconductor design principles are required.
Location: Kolkata
Experience: 4+ Years
Employment Type: Full-Time
Responsibilities :
Develop transistor-level custom layouts.
Perform floorplanning, routing, device matching, and layout optimization.
Run and resolve DRC, LVS, ERC, and extraction issues.
Coordinate with circuit designers for PPA and reliability improvements.
Requirements :
B.Tech/M.Tech in Electronics, Electrical Engineering, VLSI, or a related field.
Strong experience with Cadence Virtuoso and physical verification tools.
Good understanding of CMOS layout and advanced technology nodes.
Experience in memory or analog layout is preferred.
Scripting knowledge is an advantage.
📩 Apply or Refer:
Send your CV to hr@nexticrontechnologies.com
#NextiCron #Hiring #VLSIJobs #SemiconductorJobs #SRAM #MemoryCompiler #MemoryDesign #CustomLayout #MemoryLayout #CircuitDesign #LayoutEngineer #DesignEngineer #StaffEngineer #PrincipalEngineer #BangaloreJobs #NoidaJobs #HyderabadJobs
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NextiCron Technologies is expanding its custom IC layout team. We are looking for a VLSI Layout Design Engineer with at least four years of experience in custom IC layout. Strong expertise in physical layout design and a good understanding of semiconductor design principles are required.
Location: Kolkata
Experience: 4+ Years
Employment Type: Full-Time
Responsibilities :
Develop transistor-level custom layouts.
Perform floorplanning, routing, device matching, and layout optimization.
Run and resolve DRC, LVS, ERC, and extraction issues.
Coordinate with circuit designers for PPA and reliability improvements.
Requirements :
B.Tech/M.Tech in Electronics, Electrical Engineering, VLSI, or a related field.
Strong experience with Cadence Virtuoso and physical verification tools.
Good understanding of CMOS layout and advanced technology nodes.
Experience in memory or analog layout is preferred.
Scripting knowledge is an advantage.
📩 Apply or Refer:
Send your CV to hr@nexticrontechnologies.com
#NextiCron #Hiring #VLSIJobs #SemiconductorJobs #SRAM #MemoryCompiler #MemoryDesign #CustomLayout #MemoryLayout #CircuitDesign #LayoutEngineer #DesignEngineer #StaffEngineer #PrincipalEngineer #BangaloreJobs #NoidaJobs #HyderabadJobs
Show more Show less