C
VLSI - DFT Architect
Accepting applicationsCapgemini · Bengaluru, Karnataka, India
Full-Time Mid_senior ATPGDFTJTAGMentorPerl
Estimated market salary
₹14-25 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
2d ago
Category
Test
Experience
Mid_senior
Country
India
Roles & Responsibilities
We are seeking an experienced SoC Design-for-Test (DFT) Lead to drive DFT architecture, implementation, verification, and silicon bring-up activities for complex SoCs. The ideal candidate will possess strong expertise in scan compression, ATPG, JTAG/iJTAG, MBIST, and test integration methodologies, while leading cross-functional teams through the complete DFT lifecycle from architecture definition to production test support.
Key Responsibilities
Technical Leadership
Lead DFT execution across multiple IPs and SoC programs.
Mentor junior engineers and provide technical guidance on DFT best practices.
Collaborate effectively with Design, Verification, Physical Design, Product Engineering, and Manufacturing teams.
Participate in design reviews, architecture discussions, and project planning activities.
Develop automation flows using Perl, Shell, TCL, or Python scripting.
Collaborate with EDA vendors and internal methodology teams to improve productivity and test quality.
DFT Architecture and Implementation
Define and implement comprehensive DFT strategies for complex SoC designs.
Architect and deploy Scan, ATPG, JTAG (IEEE 1149.x), IEEE 1500, IEEE 1687 (iJTAG), Scan Compression (EDT), MBIST, and advanced test infrastructures.
Drive scan insertion and DFT implementation using Synopsys Fusion Compiler or equivalent industry-standard EDA tools.
Develop and review DFT specifications, test architectures, and verification plans.
Develop and validate STA constraints for various DFT modes.
ATPG and Test Development
Generate high-quality ATPG patterns for stuck-at, transition, path delay, and bridge fault coverage.
Perform ATPG coverage analysis, DRC closure, and optimization to achieve production test goals.
Debug and resolve ATPG, scan chain, compression, and pattern-related issues.
Validate ATPG patterns using simulation/debug environments.
Test Integration and Debug
Investigate and root-cause silicon and tester failures, partnering closely with RTL, physical design, verification, and product engineering teams.
Analyze compressed ATPG, MBIST, JTAG/IEEE1500, and iJTAG related failures.
Support silicon bring-up, characterization, production ramp, and yield improvement activities.
Drive test escape analysis and corrective action implementation.
Soft Skills
Excellent communication and stakeholder management skills.
Strong problem-solving and analytical abilities.
Proven ability to lead technical teams and drive execution across geographically distributed teams.
Ability to influence architecture and methodology decisions across organizations.
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We are seeking an experienced SoC Design-for-Test (DFT) Lead to drive DFT architecture, implementation, verification, and silicon bring-up activities for complex SoCs. The ideal candidate will possess strong expertise in scan compression, ATPG, JTAG/iJTAG, MBIST, and test integration methodologies, while leading cross-functional teams through the complete DFT lifecycle from architecture definition to production test support.
Key Responsibilities
Technical Leadership
Lead DFT execution across multiple IPs and SoC programs.
Mentor junior engineers and provide technical guidance on DFT best practices.
Collaborate effectively with Design, Verification, Physical Design, Product Engineering, and Manufacturing teams.
Participate in design reviews, architecture discussions, and project planning activities.
Develop automation flows using Perl, Shell, TCL, or Python scripting.
Collaborate with EDA vendors and internal methodology teams to improve productivity and test quality.
DFT Architecture and Implementation
Define and implement comprehensive DFT strategies for complex SoC designs.
Architect and deploy Scan, ATPG, JTAG (IEEE 1149.x), IEEE 1500, IEEE 1687 (iJTAG), Scan Compression (EDT), MBIST, and advanced test infrastructures.
Drive scan insertion and DFT implementation using Synopsys Fusion Compiler or equivalent industry-standard EDA tools.
Develop and review DFT specifications, test architectures, and verification plans.
Develop and validate STA constraints for various DFT modes.
ATPG and Test Development
Generate high-quality ATPG patterns for stuck-at, transition, path delay, and bridge fault coverage.
Perform ATPG coverage analysis, DRC closure, and optimization to achieve production test goals.
Debug and resolve ATPG, scan chain, compression, and pattern-related issues.
Validate ATPG patterns using simulation/debug environments.
Test Integration and Debug
Investigate and root-cause silicon and tester failures, partnering closely with RTL, physical design, verification, and product engineering teams.
Analyze compressed ATPG, MBIST, JTAG/IEEE1500, and iJTAG related failures.
Support silicon bring-up, characterization, production ramp, and yield improvement activities.
Drive test escape analysis and corrective action implementation.
Soft Skills
Excellent communication and stakeholder management skills.
Strong problem-solving and analytical abilities.
Proven ability to lead technical teams and drive execution across geographically distributed teams.
Ability to influence architecture and methodology decisions across organizations.
Show more Show less