VLSI CAD Engineer – SoC IP Enablement & Fron-End TFM

VLSI CAD Engineer – SoC IP Enablement & Fron-End TFM (3–6 Years Experience)
Location
Bangalore (Onsite)
Job Summary
We are looking for a highly motivated and technically strong VLSI CAD Engineer with 3–6 years of industry experience in Foundation & complex third-party IP enablement, IP collateral management & PPA studies, EDA flow support related to SOC front-end design. The ideal candidate will work closely with SoC design, CAD-Infra, methodology, and EDA vendors to enable robust and scalable IP interface and design flows across multiple projects.
This role requires strong understanding of Foundation and Complex IP components, enablement and integration challenges at different technology nodes, hands-on experience with front-end EDA tools, ability to manage IP collateral, and overall design environment deployment.


Key Responsibilitie
sEnable and integrate Foundation IPs and complex third-party IPs into SoC environments. Develop and maintain standard process and infrastructure related to collateral quality, sanity and automated validation
.Collaborate with Front-end and DFT teams on different Flow and Methodology support areas (E.g. RTL development, lint, CDC/RDC, synthesis, formal verification, and low-power methodologies, DFT stitching
)Collaborate with design, verification and physical design teams to ensure smooth adoption of design methodologies and flows
.Collaborate with EDA vendors, Library/IP providers, Foundry interface to solve a range of engineering issues related to Foundation IP, Complex IP and Front-end Flows
.Participate in methodology improvements and flow qualification for new technology nodes, PPA studies and benchmarking with different IP/Library configurations
.Support IP packaging, version control, release management, and integration workflows
.Support Python, Perl, Tcl, Makefile based automation wherever necessary

.
Required Skills & Qualificatio
nsEducational Qualificati
onB.Tech / M.Tech i
n:Electronics & Communication Engineering (EC
E)VLSI Design/Microelectroni
csStrong academic background (Tier-1 institutes) is preferre
d.Experien
ce3–6 years of relevant experience in VLSI CAD, handling third-party Foundation and Complex IP eco-system challenges, SoC design enablement, or front-end methodology developmen
t.Technical Skil
lsStrong understanding o
f:SoC front-end design flo
wsRTL-to-GDSII methodology (front-end focu
s)IP enablement, collateral management and integrati
onHands on experience with relevant Synopsys/Cadence/Siemens tools and flo

ws
Preferred Qualificati
onsExperience in complex SoC programs or semiconductor product compani
es.Exposure to advanced technology nod
es.Knowledge of CI/CD and DevOps concepts applied to semiconductor workflo
ws.Good communication and stakeholder coordination skil

ls.
Key Competen
ciesProblem-solving min
dsetStrong debugging and analytical sk
illsOwnership and accountabi
lityProcess-oriented with strong attention to de

tail
Why Jo
in UsOpportunity to work on cutting-edge SoC programs and advanced semiconductor technolo
gies.Exposure to complex IP ecosystems and enterprise-scale CAD infrastruc
ture.Collaborative environment with strong focus on innovation and automa
tion.Excellent growth opportunities in SOC methodology and CAD enginee

ring.
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