MT
Verification Lead
Accepting applicationsMulya Technologies · Greater Hyderabad Area
Full-Time Mid_senior ARMCadenceDDREthernetPCIE
Estimated market salary
₹49-89 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
23h ago
Category
Verification
Experience
Mid_senior
Country
India
DV Lead
Among. The top 4 IT companies, in India ranked by market capitalization and revenue
Bangalore /Hyderabad / Kochi
DV lead:
· 11+ years of hands-on DV experience in System Verilog/UVM.
· Must be able to own and drive the verification of a block / subsystem or a SOC.
· Should have a track record of leading a team of engineers.
· Extensive experience in IP/sub-system and/or SoC level verification based on SV/UVM.
· Experience in Test plan and Testbench development,
· Execution of test plan using high quality constrained random UVM tests to hit coverage goals on time.
· Should be good with debugging and exposed to all aspects of verification flow including Gatesims
· Must have extensive experience in verification of one or more of the following:
o PCI Express or UCIe, CXL or NVMe
o AXI, ACE or CHI
o Ethernet, RoCE or RDMA
o DDR or LPDDR or HBM
o ARM or RISC-V CPU based subsystem or SOC level verification using C/Assembly languages
o Power Aware Simulations using UPF
· Experience in using one or more of EDA tools such as VCS, Verdi, Cadence Xcelium, Simvision, Jasper.
· Experience in using one or more of revision control systems such as: Git, Perforce, Clearcase.
· Experience in SVA and formal verification is desirable (not a must)
· Script development using Python, Perl or TCL is desirable (not a must)
Skills
Systemverilog
UVM
SoC
"ip verification"
PCIE
UCIE
CXL
NVMe
CHI
Ethernet
ROCE
RDMA
DDR7
LPDDR5
HBM
ARM
RISC-V
C
Assembly
"power aware"
Jasper
Contact
Uday
muday_bhaskar@yahoo.com
Mulya Technologies
"Mining the Knowledge Community"
Show more Show less
Among. The top 4 IT companies, in India ranked by market capitalization and revenue
Bangalore /Hyderabad / Kochi
DV lead:
· 11+ years of hands-on DV experience in System Verilog/UVM.
· Must be able to own and drive the verification of a block / subsystem or a SOC.
· Should have a track record of leading a team of engineers.
· Extensive experience in IP/sub-system and/or SoC level verification based on SV/UVM.
· Experience in Test plan and Testbench development,
· Execution of test plan using high quality constrained random UVM tests to hit coverage goals on time.
· Should be good with debugging and exposed to all aspects of verification flow including Gatesims
· Must have extensive experience in verification of one or more of the following:
o PCI Express or UCIe, CXL or NVMe
o AXI, ACE or CHI
o Ethernet, RoCE or RDMA
o DDR or LPDDR or HBM
o ARM or RISC-V CPU based subsystem or SOC level verification using C/Assembly languages
o Power Aware Simulations using UPF
· Experience in using one or more of EDA tools such as VCS, Verdi, Cadence Xcelium, Simvision, Jasper.
· Experience in using one or more of revision control systems such as: Git, Perforce, Clearcase.
· Experience in SVA and formal verification is desirable (not a must)
· Script development using Python, Perl or TCL is desirable (not a must)
Skills
Systemverilog
UVM
SoC
"ip verification"
PCIE
UCIE
CXL
NVMe
CHI
Ethernet
ROCE
RDMA
DDR7
LPDDR5
HBM
ARM
RISC-V
C
Assembly
"power aware"
Jasper
Contact
Uday
muday_bhaskar@yahoo.com
Mulya Technologies
"Mining the Knowledge Community"
Show more Show less