MT
Verification Lead
Accepting applicationsMulya Technologies · Greater Bengaluru Area
Full-Time Mid_senior SystemVerilogUVMARMRISC-VAI Accelerator
Estimated market salary
₹24-44 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
19h ago
Category
Verification
Experience
Mid_senior
Country
India
DV Lead
Among. The top 4 IT companies, in India ranked by market capitalization and revenue
Bangalore
DV Lead
•Responsibility for design verification of complex HPC class silicon with multiple subsystems, including ARM, RISCV Processors and AI accelerator cores, high speed interfaces, etc
•Develop design verification plan, test bench, and appropriate execution strategy to achieve high test coverage and complete verification for first pass success with optimized time schedule and resource utilization
•Collaborate with architecture, RTL, and validation teams to deliver first-pass silicon success.
•Drive end-to-end verification from test planning to coverage closure, including regression, functional/code coverage, debugging, and verification closure.
•Ability to prepare and communicate in cross-functional forums about DV progress and achievement of targets and timelines
•Contribute to verification automation and methodology improvements.
10-15 Years experience
Prefer experience in managing several SOC verification programs
Hands on experience in SystemVerilog, UVM, SVA. Knowledge of interface protocols
Masters minimum education
Contact
Uday
muday_bhaskar@yahoo.com
Mulya Technologies
"Mining the Knowledge Community"
Show more Show less
Among. The top 4 IT companies, in India ranked by market capitalization and revenue
Bangalore
DV Lead
•Responsibility for design verification of complex HPC class silicon with multiple subsystems, including ARM, RISCV Processors and AI accelerator cores, high speed interfaces, etc
•Develop design verification plan, test bench, and appropriate execution strategy to achieve high test coverage and complete verification for first pass success with optimized time schedule and resource utilization
•Collaborate with architecture, RTL, and validation teams to deliver first-pass silicon success.
•Drive end-to-end verification from test planning to coverage closure, including regression, functional/code coverage, debugging, and verification closure.
•Ability to prepare and communicate in cross-functional forums about DV progress and achievement of targets and timelines
•Contribute to verification automation and methodology improvements.
10-15 Years experience
Prefer experience in managing several SOC verification programs
Hands on experience in SystemVerilog, UVM, SVA. Knowledge of interface protocols
Masters minimum education
Contact
Uday
muday_bhaskar@yahoo.com
Mulya Technologies
"Mining the Knowledge Community"
Show more Show less