L&
Verification Engineer (IP/AMS)
Accepting applicationsLarsen & Toubro · Bengaluru, Karnataka, India
Full-Time Mid Analogmixed signal
Estimated market salary
₹23-35 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
13 Jun
Category
Verification
Experience
Mid
Country
India
Role
This exciting position in the L&T Semiconductor Technologies (LTSCT) as the Verification Engineer (AMS), will provide the individual with an opportunity to build a strong technical career in next generation semiconductor products targeted Automotives, Energy, Industrial and Communication business verticals.
Roles & Responsibilities
Handling functional verification of mixed signal designs.
Closely interacting with Analog and Digital Design teams to identify critical features, use cases and decide right strategies for signing off the verification with best quality and aligned metrics.
Setting up the Design Verification (DV) flow, introducing new methodologies, and mentoring fresh and new team members.
Responsibilities will not be limited to functional verification of IP but may also involve executing Gate level simulations, defining DV strategies for testchips, learning new protocols and actively participating in the problem solving of other DV members and teams
Show more Show less
This exciting position in the L&T Semiconductor Technologies (LTSCT) as the Verification Engineer (AMS), will provide the individual with an opportunity to build a strong technical career in next generation semiconductor products targeted Automotives, Energy, Industrial and Communication business verticals.
Roles & Responsibilities
Handling functional verification of mixed signal designs.
Closely interacting with Analog and Digital Design teams to identify critical features, use cases and decide right strategies for signing off the verification with best quality and aligned metrics.
Setting up the Design Verification (DV) flow, introducing new methodologies, and mentoring fresh and new team members.
Responsibilities will not be limited to functional verification of IP but may also involve executing Gate level simulations, defining DV strategies for testchips, learning new protocols and actively participating in the problem solving of other DV members and teams
Show more Show less
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