TG
Verification Engineer
Accepting applicationsTPI Global Solutions · Austin, TX
Contract Mid_senior CadencePerlPythonSynopsysTCL
Posted
1d ago
Category
Verification
Experience
Mid_senior
Country
United States
Hands-on experience with VC Formal (Synopsys) and/or Jasper Gold (Cadence).
Strong proficiency in System Verilog Assertions (SVA) and formal property specification.
Experience with formal verification applications: FPV, connectivity checking, register verification, equivalence checking, and coverage analysis.
Familiarity with scripting languages (TCL, Python, Perl) for flow automation.
Extensive experience in design verification with a strong focus on formal verification.
Expertise in System Verilog and UVM-based verification methodologies.
A minimum of 8–10 years of experience is required.
Show more Show less
Strong proficiency in System Verilog Assertions (SVA) and formal property specification.
Experience with formal verification applications: FPV, connectivity checking, register verification, equivalence checking, and coverage analysis.
Familiarity with scripting languages (TCL, Python, Perl) for flow automation.
Extensive experience in design verification with a strong focus on formal verification.
Expertise in System Verilog and UVM-based verification methodologies.
A minimum of 8–10 years of experience is required.
Show more Show less