PH
Verification Engineer
Accepting applicationsPrime Hiring Solutions · San Jose, CA
Full-Time Mid_senior AIASICC++DDREthernet
Posted
20h ago
Category
Verification
Experience
Mid_senior
Country
United States
🚀 Multiple Openings: Semiconductor Design Verification Engineers
📍 Location: San Jose, CA
We are hiring multiple experienced engineers to support advanced semiconductor programs involving complex SoCs, compute engines, AI accelerators, high-speed interfaces, and formal verification.
Open positions include:
1. SoC Design Verification / Performance DV Engineers
Seeking engineers with strong system-level verification and performance-validation experience across complex SoC architectures.
Key responsibilities:
Develop SoC-level validation and performance-verification strategies
Build system-level testbenches, workloads, and performance models
Analyze bottlenecks across CPU, memory hierarchy, NoC/interconnect, and accelerators
Evaluate power-versus-performance trade-offs
Debug hardware, firmware, and software interaction issues
Collaborate with architecture, RTL, verification, firmware, and software teams
Required skills:
Strong SoC-level DV or performance-validation experience
Knowledge of CPU architecture, cache and memory hierarchy, and interconnects
SystemVerilog/UVM with C, C++, or Python
Performance profiling, workload analysis, and system-level debugging
Preferred: Post-silicon bring-up, AI/ML accelerators, or high-performance computing workloads.
2. Design Verification Engineers
Seeking hands-on DV engineers to verify compute engines, accelerators, controllers, and custom internal IP blocks.
Key responsibilities:
Develop and maintain scalable UVM verification environments
Create verification plans, test cases, sequences, scoreboards, assertions, and coverage models
Perform constrained-random and directed RTL verification
Debug RTL, testbench, and regression failures
Drive functional and code coverage closure through sign-off
Required skills:
Strong SystemVerilog and UVM experience
Block-level ASIC/IP verification
Digital design and RTL fundamentals
Experience with Verdi, DVE, or equivalent debugging tools
Preferred: UPF low-power verification and AMBA AXI/AHB/APB protocols.
3. Interface Design Verification Engineers
Seeking protocol-focused DV engineers with experience verifying high-speed interface IPs.
Key responsibilities:
Verify PCIe, DDR, USB, Ethernet, or similar interface IPs
Develop UVM testbenches and integrate commercial or internal VIPs
Execute protocol-compliance, corner-case, negative, and stress testing
Debug link-training, ordering, flow-control, recovery, and data-integrity issues
Partner with design teams to ensure specification compliance and robustness
Required skills:
Strong expertise in one or more standard protocols: PCIe, DDR, USB, or Ethernet
SystemVerilog, UVM, and VIP integration
Protocol-level debugging and waveform analysis
Preferred: High-speed interfaces, SerDes, PHY-layer concepts, and protocol analyzers.
4. Formal Verification Engineers
Seeking formal verification specialists to prove design correctness and identify corner cases beyond simulation-based testing.
Key responsibilities:
Develop formal verification strategies and test plans
Write SystemVerilog Assertions and formal properties
Perform property checking, equivalence checking, and CDC/RDC analysis
Develop assumptions, constraints, abstractions, and coverage strategies
Debug counterexamples and collaborate with RTL designers on design improvements
Required skills:
Hands-on experience with JasperGold, VC Formal, or equivalent tools
Strong SVA and property-specification skills
Digital logic, RTL design, and mathematical reasoning expertise
Preferred: Low-power formal verification, CDC/RDC, security verification, and connectivity checking.
Who Should Apply
Professionals with experience in ASIC/SoC verification, SystemVerilog, UVM, SVA, coverage closure, protocol verification, performance DV, formal verification, and semiconductor debug are encouraged to apply.
📩 Please send your updated resume to [email address] with the subject line:
Application – [Role Name] – San Jose
Qualified candidates may also share the following details:
Current location
Work authorization
Availability
Preferred role
Total years of design verification experience
#Hiring #DesignVerification #SoCVerification #PerformanceDV #FormalVerification #InterfaceVerification #ASIC #SemiconductorJobs #SystemVerilog #UVM #SVA #PCIe #DDR #AMBA #JasperGold #VCFormal #SanJoseJobs #EngineeringJobs
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📍 Location: San Jose, CA
We are hiring multiple experienced engineers to support advanced semiconductor programs involving complex SoCs, compute engines, AI accelerators, high-speed interfaces, and formal verification.
Open positions include:
1. SoC Design Verification / Performance DV Engineers
Seeking engineers with strong system-level verification and performance-validation experience across complex SoC architectures.
Key responsibilities:
Develop SoC-level validation and performance-verification strategies
Build system-level testbenches, workloads, and performance models
Analyze bottlenecks across CPU, memory hierarchy, NoC/interconnect, and accelerators
Evaluate power-versus-performance trade-offs
Debug hardware, firmware, and software interaction issues
Collaborate with architecture, RTL, verification, firmware, and software teams
Required skills:
Strong SoC-level DV or performance-validation experience
Knowledge of CPU architecture, cache and memory hierarchy, and interconnects
SystemVerilog/UVM with C, C++, or Python
Performance profiling, workload analysis, and system-level debugging
Preferred: Post-silicon bring-up, AI/ML accelerators, or high-performance computing workloads.
2. Design Verification Engineers
Seeking hands-on DV engineers to verify compute engines, accelerators, controllers, and custom internal IP blocks.
Key responsibilities:
Develop and maintain scalable UVM verification environments
Create verification plans, test cases, sequences, scoreboards, assertions, and coverage models
Perform constrained-random and directed RTL verification
Debug RTL, testbench, and regression failures
Drive functional and code coverage closure through sign-off
Required skills:
Strong SystemVerilog and UVM experience
Block-level ASIC/IP verification
Digital design and RTL fundamentals
Experience with Verdi, DVE, or equivalent debugging tools
Preferred: UPF low-power verification and AMBA AXI/AHB/APB protocols.
3. Interface Design Verification Engineers
Seeking protocol-focused DV engineers with experience verifying high-speed interface IPs.
Key responsibilities:
Verify PCIe, DDR, USB, Ethernet, or similar interface IPs
Develop UVM testbenches and integrate commercial or internal VIPs
Execute protocol-compliance, corner-case, negative, and stress testing
Debug link-training, ordering, flow-control, recovery, and data-integrity issues
Partner with design teams to ensure specification compliance and robustness
Required skills:
Strong expertise in one or more standard protocols: PCIe, DDR, USB, or Ethernet
SystemVerilog, UVM, and VIP integration
Protocol-level debugging and waveform analysis
Preferred: High-speed interfaces, SerDes, PHY-layer concepts, and protocol analyzers.
4. Formal Verification Engineers
Seeking formal verification specialists to prove design correctness and identify corner cases beyond simulation-based testing.
Key responsibilities:
Develop formal verification strategies and test plans
Write SystemVerilog Assertions and formal properties
Perform property checking, equivalence checking, and CDC/RDC analysis
Develop assumptions, constraints, abstractions, and coverage strategies
Debug counterexamples and collaborate with RTL designers on design improvements
Required skills:
Hands-on experience with JasperGold, VC Formal, or equivalent tools
Strong SVA and property-specification skills
Digital logic, RTL design, and mathematical reasoning expertise
Preferred: Low-power formal verification, CDC/RDC, security verification, and connectivity checking.
Who Should Apply
Professionals with experience in ASIC/SoC verification, SystemVerilog, UVM, SVA, coverage closure, protocol verification, performance DV, formal verification, and semiconductor debug are encouraged to apply.
📩 Please send your updated resume to [email address] with the subject line:
Application – [Role Name] – San Jose
Qualified candidates may also share the following details:
Current location
Work authorization
Availability
Preferred role
Total years of design verification experience
#Hiring #DesignVerification #SoCVerification #PerformanceDV #FormalVerification #InterfaceVerification #ASIC #SemiconductorJobs #SystemVerilog #UVM #SVA #PCIe #DDR #AMBA #JasperGold #VCFormal #SanJoseJobs #EngineeringJobs
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