TL
Verification Consultant
Accepting applicationsTechnical Link LLC · Austin, TX
Full-Time Principal ARMPerlPythonSoCSystemverilog
Posted
2d ago
Category
Verification
Experience
Principal
Country
United States
6 months
Start Date – August 31
Austin, TX (onsite) – San Jose can be an option for perfect candidate
Pay Rate - $93/hr
Must Be W-2
Must Have
Gate Level Simulation Ownership is most important….needs to have this experience.
UVM/System Verilog Experience
High performance computing background would be a huge +…someone from AMD, Qualcomm, etc
AXI/CHI protocols
Position Details
Vertical Description
Technical
As a Senior Staff System IP Design Verification Contractor you will contribute to the functional verification of System IP including coherent interconnect and caches. This is a technical individual contributor role with heavily involved hands-on project execution. A strong background in Design Verification and hands-on experience with both block-level and top-level is required to be successful in this role.
Key Responsibilities Include
Owning Gate-level simulations TB bringup
Owning power-aware verification with UPF
Collaborating with Physical design teams, running and debugging gate-level simulations
Working with SoC team to debug functional fails during IP bringup and feature execution
Creating test benches, verification environments, stimulus, tests
Collaborating with designers to verify the correctness of a design feature, and resolve fails
Developing assertions, checkers, covergroups, Systemverilog constraints
Debugging and root causing functional fails from regressions
Analyzing code and functional coverage results, performing gap analysis
Helping with Silicon bringup and root causing fails
Requirements
PhD/MS/BS in Electrical or Computer Engineering
12+ years industry experience in a design verification role
Expert hands-on coding skills in Testbench, Stimulus, checkers development, coverage closure.
Experience with System Verilog, UVM or equivalent
Atleast 5+yrs of experience with Gate-Level simulations
Knowledge of ARM protocols or equivalent protocols – CHI, AXI, ACElite, APB
Experience with Git version control, Unix/Perl/Python scripting
Good written and verbal communication skills
Show more Show less
Start Date – August 31
Austin, TX (onsite) – San Jose can be an option for perfect candidate
Pay Rate - $93/hr
Must Be W-2
Must Have
Gate Level Simulation Ownership is most important….needs to have this experience.
UVM/System Verilog Experience
High performance computing background would be a huge +…someone from AMD, Qualcomm, etc
AXI/CHI protocols
Position Details
Vertical Description
Technical
As a Senior Staff System IP Design Verification Contractor you will contribute to the functional verification of System IP including coherent interconnect and caches. This is a technical individual contributor role with heavily involved hands-on project execution. A strong background in Design Verification and hands-on experience with both block-level and top-level is required to be successful in this role.
Key Responsibilities Include
Owning Gate-level simulations TB bringup
Owning power-aware verification with UPF
Collaborating with Physical design teams, running and debugging gate-level simulations
Working with SoC team to debug functional fails during IP bringup and feature execution
Creating test benches, verification environments, stimulus, tests
Collaborating with designers to verify the correctness of a design feature, and resolve fails
Developing assertions, checkers, covergroups, Systemverilog constraints
Debugging and root causing functional fails from regressions
Analyzing code and functional coverage results, performing gap analysis
Helping with Silicon bringup and root causing fails
Requirements
PhD/MS/BS in Electrical or Computer Engineering
12+ years industry experience in a design verification role
Expert hands-on coding skills in Testbench, Stimulus, checkers development, coverage closure.
Experience with System Verilog, UVM or equivalent
Atleast 5+yrs of experience with Gate-Level simulations
Knowledge of ARM protocols or equivalent protocols – CHI, AXI, ACElite, APB
Experience with Git version control, Unix/Perl/Python scripting
Good written and verbal communication skills
Show more Show less