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Validation Engineer
Accepting applicationsProxelera · Hyderabad, Telangana, India
Full-Time Entry AIASICEthernetFPGAPCIE
Estimated market salary
₹7-13 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
5d ago
Category
Design
Experience
Entry
Country
India
Job Title
Verification Engineer-
Location
Hyderabad, Telangana
Primary Skills
System verilog,UVM,Vivado
Job Description
Location: Hyderabad
No. Of positions: 1
Experience required: 1-3 years
Job Requirements:
Will be responsible for verification of Xilinx Software Tools and flows
Work closely with various teams and cross site stakeholders to understand the requirements and deliverables
Test planning and execution for end-to-end system creation including h/w configuration on board
Develop verification methodologies for efficient testing, focused towards finding critical defects in a timely and cost-effective manner with proper escalations and reporting
Strong expertise in debugging and root-cause analysis, reporting failures, problem recreation and verification of the fixes
Develop Test plan and unit level testcases to validate the new software features. Create an automation environment to maintain the quality of test tools up-to the mark
Work with different stake holders to plan and execute the validation methodology for the Xilinx Tools and to enhance the software development process
Skills Requirements:
Understanding of Xilinx Vivado and Vitis tools is preferred
Self-driven, motivated, results oriented individual with superior academic achievements
BS in ECE or equivalent or MS in ECE.
Understanding of FPGA/ASIC designs and verification flow
Understanding of Xilinx FPGA architecture and tool flow
Good understanding of logic design and HDL (Verilog/SV/VHDL)
Good debugging skills with digital design and automation flow
Expertise and hand-on with creating efficient automation and maintaining the high coverage regression suite to keep the quality intact.
Protocol knowledge - SPI, IIC, PCIE, Ethernet, USB, HDMI would be an advantage.
Additional Requirements:
Debug of failures –Involving multiple components of the software and/or interaction of hardware, IPs, simulation etc.
Expertise in scripting and good knowledge in PERL/TCL/C-Shell.
Strong on-board debugging skill
Interface knowledge - AXI, GT, DDR4 (JEDEC).
Comments for Recruiters to be considered during screening profiles:
Strong Vivado experience required
1-3 years of experience required
AI tools preferred
Show more Show less
Verification Engineer-
Location
Hyderabad, Telangana
Primary Skills
System verilog,UVM,Vivado
Job Description
Location: Hyderabad
No. Of positions: 1
Experience required: 1-3 years
Job Requirements:
Will be responsible for verification of Xilinx Software Tools and flows
Work closely with various teams and cross site stakeholders to understand the requirements and deliverables
Test planning and execution for end-to-end system creation including h/w configuration on board
Develop verification methodologies for efficient testing, focused towards finding critical defects in a timely and cost-effective manner with proper escalations and reporting
Strong expertise in debugging and root-cause analysis, reporting failures, problem recreation and verification of the fixes
Develop Test plan and unit level testcases to validate the new software features. Create an automation environment to maintain the quality of test tools up-to the mark
Work with different stake holders to plan and execute the validation methodology for the Xilinx Tools and to enhance the software development process
Skills Requirements:
Understanding of Xilinx Vivado and Vitis tools is preferred
Self-driven, motivated, results oriented individual with superior academic achievements
BS in ECE or equivalent or MS in ECE.
Understanding of FPGA/ASIC designs and verification flow
Understanding of Xilinx FPGA architecture and tool flow
Good understanding of logic design and HDL (Verilog/SV/VHDL)
Good debugging skills with digital design and automation flow
Expertise and hand-on with creating efficient automation and maintaining the high coverage regression suite to keep the quality intact.
Protocol knowledge - SPI, IIC, PCIE, Ethernet, USB, HDMI would be an advantage.
Additional Requirements:
Debug of failures –Involving multiple components of the software and/or interaction of hardware, IPs, simulation etc.
Expertise in scripting and good knowledge in PERL/TCL/C-Shell.
Strong on-board debugging skill
Interface knowledge - AXI, GT, DDR4 (JEDEC).
Comments for Recruiters to be considered during screening profiles:
Strong Vivado experience required
1-3 years of experience required
AI tools preferred
Show more Show less