NI
Validation Engineer
Accepting applicationsnetPolarity, Inc. (Saicon Consultants, Inc.) · San Jose, CA
Contract Mid_senior FPGAPCIEPerlPythonSERDES
Posted
6d ago
Category
Test
Experience
Mid_senior
Country
United States
Title: SerDes Validation Engineer
Location: San Jose, CA (On-Site)
Duration: 12+ months contract
KEY RESPONSIBILITIES:
Develops characterization and silicon validation plans for high speed transceivers
Defines methodologies for characterization and silicon validation of high speed serial systems
Characterize high speed SERDES with automated flows
Data analysis and create characterization reports
Correlation of pre-silicon results with silicon measurements
Drives direct and cross-functional teams to expand capability, productivity and effectiveness to deliver improvements in cost, quality and manufacturability
PREFERRED EXPERIENCE:
Experience in characterizing analog front-end
PLL phase noise measurement, traPLL, CDR, TX/RXnsmitter output jitter measurement, receiver jitter tolerance measurement
Hands on experience in laboratory environment, using lab equipment such as sampling oscilloscope, high performance BERT, logic analyzers, spectrum analyzers, BERT scopes, function/pulse generator
Experience in transceiver electrical compliance testing (PCIE, IEEE 802.3, OIF-CEI)
Experience in using automated methodologies to maximize use of equipment
Experience working with FPGA and/or SOC Architectures
Understanding of PCB schematic and layout
Strong analytical, problem-solving and debugging skills
Experience in protocol testing (PCIE, SATA, SGMII, 100GBASE-X)
Skills: Verilog, Python, Perl, TCL
ACADEMIC CREDENTIALS:
BSEE/MSEE with 0-2 years of experience in product characterization or validation field
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Location: San Jose, CA (On-Site)
Duration: 12+ months contract
KEY RESPONSIBILITIES:
Develops characterization and silicon validation plans for high speed transceivers
Defines methodologies for characterization and silicon validation of high speed serial systems
Characterize high speed SERDES with automated flows
Data analysis and create characterization reports
Correlation of pre-silicon results with silicon measurements
Drives direct and cross-functional teams to expand capability, productivity and effectiveness to deliver improvements in cost, quality and manufacturability
PREFERRED EXPERIENCE:
Experience in characterizing analog front-end
PLL phase noise measurement, traPLL, CDR, TX/RXnsmitter output jitter measurement, receiver jitter tolerance measurement
Hands on experience in laboratory environment, using lab equipment such as sampling oscilloscope, high performance BERT, logic analyzers, spectrum analyzers, BERT scopes, function/pulse generator
Experience in transceiver electrical compliance testing (PCIE, IEEE 802.3, OIF-CEI)
Experience in using automated methodologies to maximize use of equipment
Experience working with FPGA and/or SOC Architectures
Understanding of PCB schematic and layout
Strong analytical, problem-solving and debugging skills
Experience in protocol testing (PCIE, SATA, SGMII, 100GBASE-X)
Skills: Verilog, Python, Perl, TCL
ACADEMIC CREDENTIALS:
BSEE/MSEE with 0-2 years of experience in product characterization or validation field
Show more Show less