AN
UVM Lead Verification Engineer
Accepting applicationsArtha Nexgen · Seattle, WA
Full-Time Lead ATEUVMVHDLVerilogate
Posted
3d ago
Category
Verification
Experience
Lead
Country
United States
Job Description
Location: Redmond, Seattle, Washington
Experience: 8-15 years
Onsite: YES @ customer location
Duration; Long Term
Full time rate: 170k
Visa: USC and GC
ONLY LOCAL CANDIDATES PLEASE
Jd
He should have some lead experience, even hands on experience in also fine.
Design Verification expertise in System Verilog /UVM for Unit/Module level Verification
Should have Lead Design Verification Team ( Min 5 Members)
Strong background in developing UVM Testbenches from scratch
Experience in VIP Integration and Bring up
Porting Existing Verilog/VHDL environment to UVM based Environment
Experience in test planning ,Coverage Coding and Debugging
Deep Knowledge of AMBA Protocol is must
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Job Overview
Date Posted:
29-01-2026
Location: Redmond, Seattle, Washington
Job Title
UVM Lead Verification Engineer
Work Experience
8
Salary
USD $170k Annually
Show more Show less
Location: Redmond, Seattle, Washington
Experience: 8-15 years
Onsite: YES @ customer location
Duration; Long Term
Full time rate: 170k
Visa: USC and GC
ONLY LOCAL CANDIDATES PLEASE
Jd
He should have some lead experience, even hands on experience in also fine.
Design Verification expertise in System Verilog /UVM for Unit/Module level Verification
Should have Lead Design Verification Team ( Min 5 Members)
Strong background in developing UVM Testbenches from scratch
Experience in VIP Integration and Bring up
Porting Existing Verilog/VHDL environment to UVM based Environment
Experience in test planning ,Coverage Coding and Debugging
Deep Knowledge of AMBA Protocol is must
Share this job
Facebook Twitter Google+
Job Overview
Date Posted:
29-01-2026
Location: Redmond, Seattle, Washington
Job Title
UVM Lead Verification Engineer
Work Experience
8
Salary
USD $170k Annually
Show more Show less