ST
UFS Verification Engineer
Accepting applicationsScaledge Technology · Bengaluru, Karnataka, India
Full-Time Mid_senior ASICSoCSystemVerilogUVMVLSI
Posted
3d ago
Category
Verification
Experience
Mid_senior
Country
India
🚀 Hiring: UFS Verification Specialist (5+ Years Experience)
📍 Location: Bangalore
💼 Experience: 5+ Years
We are actively looking for experienced UFS Design Verification (DV) Engineers to join a leading VLSI team working on next-generation UFS (Universal Flash Storage) IP/SoC solutions.
Key Responsibilities
*) Develop and execute comprehensive verification plans for UFS IP/Subsystems.
*) Create and maintain SystemVerilog/UVM-based verification environments.
*) Develop test cases, assertions, checkers, scoreboards, and coverage models.
*) Debug complex functional issues and work closely with design teams for resolution.
*) Perform protocol-level verification of UFS, UniPro, M-PHY, and related interfaces.
*) Analyze simulation results, coverage metrics, and drive closure activities.
*) Collaborate with architecture, design, firmware, and validation teams throughout the product lifecycle.
*) Support regression execution and improve verification methodologies and automation.
Required Skills
*) Bachelor's/Master's degree in Electronics, Electrical Engineering, or related field.
*) 5+ years of experience in ASIC/SoC Design Verification.
*) Strong expertise in SystemVerilog and UVM methodology.
*) Experience in developing verification environments from scratch.
*) Strong debugging and problem-solving skills.
*) Knowledge of functional coverage, assertions (SVA), and verification planning.
*) Experience with industry-standard simulators and verification tools.
📩 Interested candidates can share their resumes at erum@scaledge.io
Show more Show less
📍 Location: Bangalore
💼 Experience: 5+ Years
We are actively looking for experienced UFS Design Verification (DV) Engineers to join a leading VLSI team working on next-generation UFS (Universal Flash Storage) IP/SoC solutions.
Key Responsibilities
*) Develop and execute comprehensive verification plans for UFS IP/Subsystems.
*) Create and maintain SystemVerilog/UVM-based verification environments.
*) Develop test cases, assertions, checkers, scoreboards, and coverage models.
*) Debug complex functional issues and work closely with design teams for resolution.
*) Perform protocol-level verification of UFS, UniPro, M-PHY, and related interfaces.
*) Analyze simulation results, coverage metrics, and drive closure activities.
*) Collaborate with architecture, design, firmware, and validation teams throughout the product lifecycle.
*) Support regression execution and improve verification methodologies and automation.
Required Skills
*) Bachelor's/Master's degree in Electronics, Electrical Engineering, or related field.
*) 5+ years of experience in ASIC/SoC Design Verification.
*) Strong expertise in SystemVerilog and UVM methodology.
*) Experience in developing verification environments from scratch.
*) Strong debugging and problem-solving skills.
*) Knowledge of functional coverage, assertions (SVA), and verification planning.
*) Experience with industry-standard simulators and verification tools.
📩 Interested candidates can share their resumes at erum@scaledge.io
Show more Show less