G
TPU Design Verification Engineering Lead
Accepting applicationsGoogle · Mountain View, CA
Full-Time Mid_senior AISoCUVM
Posted
3d ago
Category
Verification
Experience
Mid_senior
Country
United States
In most instances, this position requires in-person interviews as part of the hiring process.
Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Mountain View, CA, USA; San Diego, CA, USA.Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
10 years of experience in managing functional verification for IPs and SoCs.
Preferred qualifications:
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
Experience leading design verification of an SoC or large ASICs.
Experience in collaborating effectively across organization and geo boundaries to build relationships and import/export ideas to achieve a broader organizational goal.
Experience in driving cross-functional teams for high quality tape-outs.
Deep technical expertise in different verification techniques and methodologies including formal, GLS, UPF based power simulations, UVM and C based testing, to achieve bug-free Silicon in complex SoCs.
About The Job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.
US: $192000 - $278000 (USD) + 20% bonus target + equity + benefits
Responsibilities
Learn more about benefits at Google .
Act as the primary point of contact for IP and SoC functional verification for cross functional teams.
Coordinate with architecture, design teams, Sival and SW teams in defining the overall verification strategy of our SoCs.
Set the goal and own verification methodology for multiple chips.
Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .
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Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Mountain View, CA, USA; San Diego, CA, USA.Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
10 years of experience in managing functional verification for IPs and SoCs.
Preferred qualifications:
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
Experience leading design verification of an SoC or large ASICs.
Experience in collaborating effectively across organization and geo boundaries to build relationships and import/export ideas to achieve a broader organizational goal.
Experience in driving cross-functional teams for high quality tape-outs.
Deep technical expertise in different verification techniques and methodologies including formal, GLS, UPF based power simulations, UVM and C based testing, to achieve bug-free Silicon in complex SoCs.
About The Job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.
US: $192000 - $278000 (USD) + 20% bonus target + equity + benefits
Responsibilities
Learn more about benefits at Google .
Act as the primary point of contact for IP and SoC functional verification for cross functional teams.
Coordinate with architecture, design teams, Sival and SW teams in defining the overall verification strategy of our SoCs.
Set the goal and own verification methodology for multiple chips.
Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .
Show more Show less