Test Chip Physical Design (Digital) Engineer

Location: Albany (NY)--preferred, Santa Clara (CA), or Tokyo (Japan)

-Role Overview:

This role focuses on the physical implementation of digital test chips used to validate Rapidus’s 2nm capabilities.

You will manage the end-to-end RTL-to-GDS design process for logic-based test chips dedicated to monitoring PPA and yield.

A critical part of this role is to utilize and validate the internal Digital Reference Flow, providing direct feedback to the

methodology team to ensure its maturity and competitiveness.

Key Responsibilities:

・Execute the full physical design flow (RTL-to-GDS) for digital test chips.

・Design and implement test chips specifically by utilizing the Digital Reference Flow developed within Rapidus.

・Provide continuous feedback and drive improvements to the Reference Flow based on practical design experiences, identifying bottlenecks and suggesting enhancements.

・Implement logic circuits for device evaluation and characterization (e.g., monitor circuits).

・Work in tandem with EDA vendors and design partners (contractors) to ensure timely and high-quality physical implementation.

・Analyze silicon results to refine design rules and physical design parameters.

Qualifications:

・Hands-on experience in RTL-to-GDS physical design and implementation.

・Experience with advanced process nodes (7nm FinFET and beyond) is preferred but not mandatory.

・Ability to analyze design flows and propose technical improvements.

・Proven ability to collaborate with external stakeholders, including EDA vendors and design service partners.