Technical Manager – DFT

Technical Manager – DFT
Location: Bengaluru
Experience: 12–18 Years
About the Role:
We are seeking a highly technical DFT Manager to lead DFT architecture and execution for complex, high-performance SoCs targeted for AI, Datacenter, Networking, and Compute applications. This role requires deep expertise in advanced DFT methodologies, strong debugging capability, and hands-on ownership from architecture definition through silicon bring-up while mentoring and technically leading a team.
Responsibilities:
Define and drive SoC DFT architecture for complex ASIC/SoC designs.
Lead scan insertion, compression, ATPG, MBIST, LBIST, JTAG and IJTAG implementation and signoff.
Drive hierarchical, low-power and physical-aware DFT methodologies.
Own fault coverage closure, diagnosis, silicon debug, and yield improvement.
Collaborate with RTL, PD, STA, and Post-Silicon teams to ensure DFT convergence and tapeout readiness.
Mentor and provide technical leadership to DFT engineers across multiple projects.
Requirements:
12–18 years of hands-on DFT experience with multiple successful SoC tapeouts.
Strong expertise in Scan Compression, ATPG, MBIST, LBIST, IEEE 1149.1, IEEE 1500 and IEEE 1687.
Hands-on experience with Mentor Tessent and/or Synopsys DFTMAX/TestMAX flows.
Solid understanding of low-power DFT, timing constraints, and physical-aware DFT methodologies.
Proficiency in Verilog/SystemVerilog, Tcl, Perl/Python, and Linux environments.
Experience with advanced nodes (7nm/5nm/3nm) and large hierarchical SoCs is highly desirable.
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