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Technical Lead I - VLSI
Accepting applicationsUST · Bengaluru, Karnataka, India
Full-Time Mid_senior DDRSystemVerilogVLSIVerilogddr
Posted
4d ago
Category
Verification
Experience
Mid_senior
Country
India
Role Description
Job Description: Formal Verification Engineer KEY RESPONSIBILITIES:Verification of Test Chips and DDRPHY: Connectivity verification for Test chips, Block level property verification for DDR PHY along with other use cases. Good understanding of Formal property verification, In-depth knowledge in formal verification algorithms, engines and use casesProven expertise in system Verilog assertion and abstract model developmentProven expertise in developing formal verification infrastructure for FPV, DPV, SEQ and other use cases is strongly preferredContributes to test plan development. Experience required: 5-8 years of experience Language : SystemVerilog and SVA (System Verilog Assertions)
Skills
vlsi design,block level property verification,formal verification,test chips,ddrphy,connectivity verification,
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Job Description: Formal Verification Engineer KEY RESPONSIBILITIES:Verification of Test Chips and DDRPHY: Connectivity verification for Test chips, Block level property verification for DDR PHY along with other use cases. Good understanding of Formal property verification, In-depth knowledge in formal verification algorithms, engines and use casesProven expertise in system Verilog assertion and abstract model developmentProven expertise in developing formal verification infrastructure for FPV, DPV, SEQ and other use cases is strongly preferredContributes to test plan development. Experience required: 5-8 years of experience Language : SystemVerilog and SVA (System Verilog Assertions)
Skills
vlsi design,block level property verification,formal verification,test chips,ddrphy,connectivity verification,
Show more Show less