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Technical Lead I - VLSI AL SD
Accepting applicationsUST · Bengaluru, Karnataka, India
Full-Time Mid_senior AnalogCadenceCalibreVLSIcadence
Estimated market salary
₹23-41 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
5d ago
Category
Design
Experience
Mid_senior
Country
India
Role Description
Analog Layout
Candidate should work independently on block level and chip level Analog layout design, coordinating with the circuit designer & the project lead.
Candidate should have minimum 5+ years of hands-on experience in Analog layout.
Custom layout experience in DAC, ADC, Band gap, Regulators, LDOs etc.
Knowledge of finfet or technology exposure to 28nm or below is an added advantage.
Full Understanding of IC fabrication and reliability issues.
Full familiarity with Cadence-Virtuoso, PVS, ASSURA and Calibre tools.
Outstanding written and verbal communication skills.
Skills
vlsi design,cadence virtuoso,calibre,finfet,
Show more Show less
Analog Layout
Candidate should work independently on block level and chip level Analog layout design, coordinating with the circuit designer & the project lead.
Candidate should have minimum 5+ years of hands-on experience in Analog layout.
Custom layout experience in DAC, ADC, Band gap, Regulators, LDOs etc.
Knowledge of finfet or technology exposure to 28nm or below is an added advantage.
Full Understanding of IC fabrication and reliability issues.
Full familiarity with Cadence-Virtuoso, PVS, ASSURA and Calibre tools.
Outstanding written and verbal communication skills.
Skills
vlsi design,cadence virtuoso,calibre,finfet,
Show more Show less
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