CI
Systems/Algorithms Engineer - Clock and Data Recovery
Accepting applicationsCspeedIO, Inc. · Palo Alto, CA
Full-Time Mid_senior AIC++EthernetMATLABPCIe
Posted
26 May
Category
Test
Experience
Mid_senior
Country
United States
Cspeed IO is a stealth start up backed by Sutter Hills Ventures and Atreides Capital - headquartered in Palo Alto, CA. Our executive team has a demonstrated track record of building and scaling category-defining semiconductor and infrastructure businesses at companies like Broadcom, Lumentum, Tesla, Apple, Samsung, Intel, and VMware.
Cspeed IO is developing next-generation optical semiconductor solutions for the AI infrastructure market, focused on enabling true “scale-up” architectures. Our mission is to replace traditional copper interconnects with advanced fiber-optic technologies that overcome the limitations of existing optics solutions and architectures.
We are seeking a Systems/Algorithms Engineer with experience in serial communication links. This role is central to bridging system-level design with hardware implementation, working on Clock and Data Recovery (CDR) systems that enable reliable high-speed data transmission.
Key Responsibilities
Architect Clock and Data Recovery (CDR) systems and similar communication links
Collaborate closely with RTL and analog circuit designers to define specifications for building blocks
Provide system-level tradeoff analysis (power, performance, area, latency) to guide design choices
Model hardware non-idealities, simulate, and validate system performance
Oversee implementation to ensure functionality and optimal performance
Develop, improve, and maintain bit-true models
Document and communicate architectural specifications to cross-functional teams
Required Qualifications
Master's or PhD in Electrical Engineering, Computer Engineering, or related field
Minimum 5 years of industry experience
Strong background in digital communication systems, particularly clock and data recovery and synchronization
Experience with bit-true modeling in MATLAB, Simulink, C++, Python, or equivalent environments
Solid understanding of high-speed SerDes systems and related algorithms, such as Forward Error Correction (FEC)
Preferred Qualifications
Experience with industry-standard protocols (PCIe, USB, Ethernet, or similar)
Familiarity with equalization techniques (FFE, DFE, CTLE)
Experience with statistical simulation methods (e.g., peak distortion analysis)
Knowledge of jitter analysis and signal integrity concepts
Track record of successful product tape-outs
Show more Show less
Cspeed IO is developing next-generation optical semiconductor solutions for the AI infrastructure market, focused on enabling true “scale-up” architectures. Our mission is to replace traditional copper interconnects with advanced fiber-optic technologies that overcome the limitations of existing optics solutions and architectures.
We are seeking a Systems/Algorithms Engineer with experience in serial communication links. This role is central to bridging system-level design with hardware implementation, working on Clock and Data Recovery (CDR) systems that enable reliable high-speed data transmission.
Key Responsibilities
Architect Clock and Data Recovery (CDR) systems and similar communication links
Collaborate closely with RTL and analog circuit designers to define specifications for building blocks
Provide system-level tradeoff analysis (power, performance, area, latency) to guide design choices
Model hardware non-idealities, simulate, and validate system performance
Oversee implementation to ensure functionality and optimal performance
Develop, improve, and maintain bit-true models
Document and communicate architectural specifications to cross-functional teams
Required Qualifications
Master's or PhD in Electrical Engineering, Computer Engineering, or related field
Minimum 5 years of industry experience
Strong background in digital communication systems, particularly clock and data recovery and synchronization
Experience with bit-true modeling in MATLAB, Simulink, C++, Python, or equivalent environments
Solid understanding of high-speed SerDes systems and related algorithms, such as Forward Error Correction (FEC)
Preferred Qualifications
Experience with industry-standard protocols (PCIe, USB, Ethernet, or similar)
Familiarity with equalization techniques (FFE, DFE, CTLE)
Experience with statistical simulation methods (e.g., peak distortion analysis)
Knowledge of jitter analysis and signal integrity concepts
Track record of successful product tape-outs
Show more Show less