System Engineer - SystemC Modelling Engineer

Job Title: SystemC Modelling Engineer
Salary: Upto 25 LPA (Based on Experience)

Role Overview
Seeking a highly skilled SystemC Modelling Engineer to develop, validate, and optimize SystemC/TLM models for complex digital hardware systems. The ideal candidate should have strong expertise in SystemC, C/C++, computer architecture, and simulation methodologies, with hands-on experience in modeling processors, memory subsystems, interconnects, and SoC architectures.
The role involves close collaboration with hardware architects, RTL designers, software teams, and verification engineers to enable early architecture validation, performance analysis, and hardware/software co-simulation.

Key Responsibilities
SystemC Modelling & Development
Develop and implement SystemC models of hardware architectures and system components based on design specifications.
Create Transaction Level Models (TLM) for performance analysis and architectural exploration.
Model processors, memory systems, interconnect fabrics, bus subsystems, and SoC components.
Integrate SystemC models with simulation and verification environments.
Simulation & Verification
Develop simulation test benches to verify functionality and performance of SystemC models.
Execute simulations, analyze results, and identify architectural or design bottlenecks.
Debug SystemC models and simulation environments to ensure accuracy and reliability.
Support hardware/software co-simulation activities.
Performance Analysis
Perform architecture-level performance analysis and profiling.
Evaluate system behavior under different workloads and configurations.
Generate performance reports and recommend design improvements.
Collaboration & Documentation
Work closely with hardware architects, RTL designers, software developers, and verification teams.
Contribute to modeling methodologies, standards, and best practices.
Prepare and maintain technical documentation, simulation setups, test plans, and results.
Participate in design reviews and architecture discussions.
Required Qualifications
Bachelor's or Master's Degree in Electrical Engineering, Electronics Engineering, Computer Engineering, Computer Science, or a related discipline.
3–6 years of hands-on experience in SystemC modeling and simulation of digital hardware systems.
Required Technical Skills
Programming & Modelling
Strong proficiency in SystemC.
Strong programming skills in C/C++.
Experience developing and debugging SystemC/TLM models.
Architecture Knowledge
Strong understanding of:
Computer Architecture
Digital Logic Design
Processor Pipelines
Memory Hierarchies
RISC-V Architecture
Memory Subsystems
Bus Architectures
Interconnect Fabrics
SoC Design Concepts
Simulation & Verification
Knowledge of simulation and verification methodologies.
Experience with hardware/software co-simulation.
Familiarity with SystemC Verification (SCV) concepts.
Scripting & Automation
Experience with Python, Tcl, or similar scripting languages for automation and workflow optimization.

Preferred Qualifications
Experience with different TLM abstraction levels (LT/AT).
Familiarity with Verilog and/or VHDL.
Experience with FPGA prototyping platforms.
Exposure to architecture performance modeling and profiling.
Experience working on RISC-V based platforms.
Knowledge of advanced SoC verification and simulation flows.
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