IG
System Engineer
Accepting applicationsInfotree Global Solutions · Cupertino, CA
Contract Mid_senior DDREthernetMatlabPCIePERL
Posted
1d ago
Category
Test
Experience
Mid_senior
Country
United States
System Signal Integrity Engineer
Contract role for duration 12+ months in Cupertino, CA/Austin, TX
Candidates local to California and Texas
Description:
You should have deep knowledge and familiarity with all aspects of Signal Integrity for high speed SerDes, Parallel bus, and single ended signaling.
Key Qualifications:
The candidate must have system-level Serdes design and analysis skills.
The Serdes knowledge required includes understanding of transmitter and receiver equalization methods (including FFE, CTLE, DFE, VGA gain), CDR behaviors and modeling, link training algorithms and internal eye margining tool for NRZ, PAM3, and PAM4 signaling. Experiences on Multi-level signaling such as PAM3 and PAM4 are preferred.
Serial bus expertise shall include the knowledges and experiences in various industry Serdes standards such as USB4, DisplayPort, HDMI, MIPI, SD, USB2, Ethernet, PCIe, USB3.1, and Thunderbolt. SI skills required include a good understanding in NRZ, PAM3, and PAM4 signaling and its statistical DOE analysis across channel variants, applying equalization and training as required for end-to-end channel analysis.
Parallel bus interface expertise should include understanding of signaling specs and signal integrity signoff for DDR, GDDR, LPDDR, NAND interfaces, and common synchronous interfaces.
Experiences and knowledges on the transmitter and receiver compliance tests and passive channel/component characterization for high speed Serdes are required.
Description:
Hands-on experience with PCB and Flex layout review, including trace routing, impedance control, and return path analysis
Understanding of high-speed digital interface protocols (PCIe, USB, DisplayPort, HDMI) and their electrical specification requirement
Proficiency in channel modeling and end-to-end link simulation using industry-standard tools (Ansys HFSS, Keysight ADS, SIwave, PowerSI)
Interconnect modeling capability, using S-parameter, W-elements, etc is required. An understanding of channel types including cabling, pcb materials, flex materials, and connector design methods and limitations is required.
Relevant working knowledge of IBIS-AMI, HSPICE, Spectre, AMS, and Simplis models for system-level transient analysis is also necessary. Working knowledge of ADS is desired.
Measurement expertise with frequency and time domain tools (VNA, TDR) including calibration & deembedding experiences is desired.
Experience with Matlab/Python/PERL and other scripting languages is desired.
Excellent documentation and communication skills, ability to work independently, and demonstrated ability to innovate are required.
Education:
PhD (Preferred) with 3+ years of industry experience, or Masters (minimum) with at least 5+ years of industry experience.
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Contract role for duration 12+ months in Cupertino, CA/Austin, TX
Candidates local to California and Texas
Description:
You should have deep knowledge and familiarity with all aspects of Signal Integrity for high speed SerDes, Parallel bus, and single ended signaling.
Key Qualifications:
The candidate must have system-level Serdes design and analysis skills.
The Serdes knowledge required includes understanding of transmitter and receiver equalization methods (including FFE, CTLE, DFE, VGA gain), CDR behaviors and modeling, link training algorithms and internal eye margining tool for NRZ, PAM3, and PAM4 signaling. Experiences on Multi-level signaling such as PAM3 and PAM4 are preferred.
Serial bus expertise shall include the knowledges and experiences in various industry Serdes standards such as USB4, DisplayPort, HDMI, MIPI, SD, USB2, Ethernet, PCIe, USB3.1, and Thunderbolt. SI skills required include a good understanding in NRZ, PAM3, and PAM4 signaling and its statistical DOE analysis across channel variants, applying equalization and training as required for end-to-end channel analysis.
Parallel bus interface expertise should include understanding of signaling specs and signal integrity signoff for DDR, GDDR, LPDDR, NAND interfaces, and common synchronous interfaces.
Experiences and knowledges on the transmitter and receiver compliance tests and passive channel/component characterization for high speed Serdes are required.
Description:
Hands-on experience with PCB and Flex layout review, including trace routing, impedance control, and return path analysis
Understanding of high-speed digital interface protocols (PCIe, USB, DisplayPort, HDMI) and their electrical specification requirement
Proficiency in channel modeling and end-to-end link simulation using industry-standard tools (Ansys HFSS, Keysight ADS, SIwave, PowerSI)
Interconnect modeling capability, using S-parameter, W-elements, etc is required. An understanding of channel types including cabling, pcb materials, flex materials, and connector design methods and limitations is required.
Relevant working knowledge of IBIS-AMI, HSPICE, Spectre, AMS, and Simplis models for system-level transient analysis is also necessary. Working knowledge of ADS is desired.
Measurement expertise with frequency and time domain tools (VNA, TDR) including calibration & deembedding experiences is desired.
Experience with Matlab/Python/PERL and other scripting languages is desired.
Excellent documentation and communication skills, ability to work independently, and demonstrated ability to innovate are required.
Education:
PhD (Preferred) with 3+ years of industry experience, or Masters (minimum) with at least 5+ years of industry experience.
Show more Show less