System Architect

LOCATION: GREATER BENGALURU AREA


Company Descriptio
nWe are looking for exceptional talent and leadership to join Fast Growing Startup into Scalable Intelligence, the world’s first company developing Agentic Silicon for powering the future of AI.Founded in 2023, We have deep customer engagements across America, Europe, and Asia, and demonstrated functional prototypes to prove our concept and visi

o
.Key Link
s to IncludeOfficial Website: tsavoritesi.comLinkedIn Page
: Tsavorite Scalable Intelligenc
e | LinkedInRecent News
: Tsavorite Emerges with $100M in Orders & 10x Performance(Forbe
s)https://www.businesswire.com/news/home/20251110678526/en/Tsavorite-Scalable-

In
We are seeking a Systems Architect to drive end-to-end system definition and architecture across the full hardware spectrum—from compact Edge & Physical AI devices to high-density, multi-megawatt OCP datacenter rac
ks.In this role, you will lead System-Technology Co-Optimization (STCO) from the chip out to the datacenter, collaborating with Silicon, Advanced Packaging, Board Design, SI/PI, and Thermal/Mechanical teams. Responsible for the Optimized product solution based on the power, performance and cost of different configurations. Collaborate with key customers and system partners on the product solutio
ns.Key Responsibilit
iesEnd-to-End System Definition: Drive architecture from the silicon chip out to full datacenter deployments and edge platforms, balancing performance, power, thermals, and total cost of ownership (TC
O).STCO & Cross-Domain Co-Design: Partner across Silicon, Advanced Packaging (substrates, 2.5D/3D, BGA ball maps), PCB Design, Software, and Operations to optimize interfaces, escape routing, power delivery, and system bring-
up.Board, SI/PI & Power Architecture: Architect full-path channel envelopes for Scale-up and Scale-out solutions with data rates enveloping 112G-224G Serdes. Define high-speed multi-layer PCB solution, loss/crosstalk budgets, and Power Delivery Networks (PDN)—from edge DC inputs to 48V/54V OCP busbars and 1000A+ transient VR
Ms.Thermals & Physical Form Factors: Specify mechanical and thermal architectures across edge environments and OCP rack-scale platforms (air cooling, cold plates, and direct-to-chip liquid cooling/CDU
s).Scale-Up & Scale-Out Interconnects: Define architectures for front-panel interfaces (OSFP, QSFP-DD), high-speed backplane connectors, AECs, and AOCs/optical transceive
rs.Ecosystem & Lifecycle Leadership: Collaborate with key customers, ODMs, and component suppliers to align technology roadmaps and take systems from concept through volume producti
on.Qualifications & Ski
llsRequired Qualificati
onsExperience: 14+ years architecting complex hardware platforms, server builds, or high-speed syste
ms.High-Speed PCB & Systems: Deep expertise in high-speed, multi-layer product board design, SI/PI channel budgeting, and server-level mechanical, power, and thermal integrati
on.Interconnect Standards: 112G/224G PAM4 SerDes, PCIe Gen 5/6/7 (128 Gbps/lane), CXL, and Ethernet standa
rdsForm Factors & Cabling: Working knowledge of OCP standards (ORv3, busbars, OAM/UBB), OSFP/QSFP-DD, backplanes, AEC, and AOC solutio
ns.STCO & Problem Solving: Demonstrated success with Silicon–Package–PCB co-optimization and hands-on resolution of complex hardware/software issu
es.Leadership: Strong interpersonal skills to align multi-disciplinary teams with a proactive, learning-oriented minds
et.Education: Master's degree in computer engineering, Electrical Engineering, Computer Science, or related domai
ns.Key skil
ls:"system architectu
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Udaymuday_bhaskar@yaho
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