7S
Synthesis /Static Timing Analysis (STA) | Timing Enginner
Accepting applications7Rays Semiconductors · Greater Bengaluru Area
Full-Time Mid_senior STADMSALogical SynthesisLogical Equivalence CheckTiming Closure
Posted
3d ago
Category
Design
Experience
Mid_senior
Country
India
Position Overview:
We are seeking an experienced STA Engineer with in-depth knowledge and hands-on experience in Static Timing Analysis, Logical Synthesis, Logical Equivalence Check, and timing closure processes. The candidate will be responsible for handling timing closure at various levels, from subsystem to chip level, and must be proficient in DMSA flow for pre- and post-STA timing. The role also includes guiding and mentoring a team of 4-5 members on STA and Synthesis best practices.
Key Responsibilities:
Perform Static Timing Analysis (STA) with a strong understanding of timing constraints and timing closure across subsystem, block, and chip levels.
Conduct logical-aware synthesis and logical equivalence checks to ensure design integrity.
Utilize DMSA flow for both pre-layout and post-layout timing fixes.
Develop and refine timing constraints and manually write ECOs (Engineering Change Orders) to resolve timing violations and DRCs.
Lead timing closure activities, including:
Subsystem, block, and chip-level timing closure
Pre-layout timing analysis and reporting
Post-layout timing analysis, specifically focusing on placement, CTS, and clock gating checks
Final tape-out timing closure across multiple corners and modes
Create and modify TCL scripts for automation and ensure seamless operations within the UNIX environment.
Lead, mentor, and guide a team of 4-5 engineers, ensuring best practices in STA and Synthesis are followed.
Collaborate closely with RTL Design, Physical Design (PD), and Hardware Management (HM) teams for comprehensive SoC timing closure.
Qualifications:
Comprehensive experience in Static Timing Analysis (STA), Logical Synthesis, and Logical Equivalence Check.
Proficient with DMSA flow for timing fixes.
Strong knowledge of timing closure at subsystem, block, and chip levels.
Proficiency in writing manual ECOs for timing and DRC fixes.
Skilled in TCL scripting and UNIX.
Experience with pre-layout and post-layout timing analysis and reporting.
Proven leadership skills with experience managing a team of 4-5 members.
Excellent collaboration skills for cross-functional work with RTL, PD, and HM teams.
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We are seeking an experienced STA Engineer with in-depth knowledge and hands-on experience in Static Timing Analysis, Logical Synthesis, Logical Equivalence Check, and timing closure processes. The candidate will be responsible for handling timing closure at various levels, from subsystem to chip level, and must be proficient in DMSA flow for pre- and post-STA timing. The role also includes guiding and mentoring a team of 4-5 members on STA and Synthesis best practices.
Key Responsibilities:
Perform Static Timing Analysis (STA) with a strong understanding of timing constraints and timing closure across subsystem, block, and chip levels.
Conduct logical-aware synthesis and logical equivalence checks to ensure design integrity.
Utilize DMSA flow for both pre-layout and post-layout timing fixes.
Develop and refine timing constraints and manually write ECOs (Engineering Change Orders) to resolve timing violations and DRCs.
Lead timing closure activities, including:
Subsystem, block, and chip-level timing closure
Pre-layout timing analysis and reporting
Post-layout timing analysis, specifically focusing on placement, CTS, and clock gating checks
Final tape-out timing closure across multiple corners and modes
Create and modify TCL scripts for automation and ensure seamless operations within the UNIX environment.
Lead, mentor, and guide a team of 4-5 engineers, ensuring best practices in STA and Synthesis are followed.
Collaborate closely with RTL Design, Physical Design (PD), and Hardware Management (HM) teams for comprehensive SoC timing closure.
Qualifications:
Comprehensive experience in Static Timing Analysis (STA), Logical Synthesis, and Logical Equivalence Check.
Proficient with DMSA flow for timing fixes.
Strong knowledge of timing closure at subsystem, block, and chip levels.
Proficiency in writing manual ECOs for timing and DRC fixes.
Skilled in TCL scripting and UNIX.
Experience with pre-layout and post-layout timing analysis and reporting.
Proven leadership skills with experience managing a team of 4-5 members.
Excellent collaboration skills for cross-functional work with RTL, PD, and HM teams.
Show more Show less