Synthesis & LEC Staff

Location: Bengaluru, India Experience: 7–15 years Industry: Semiconductors | AI | Networking | ASIC Design


Job Title: Synthesis & LEC Lead/Staf

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Location: Bengaluru, India Experience: 5–15 years Industry: Semiconductors | AI | Networking | ASIC Desi

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Role Overv
iewAs the Synthesis & LEC Lead at , you will be the bridge between high-level
RTLarchitecture and physical reality. In the world of high-performance AI SOCs, the "RTL-to-Netli
st"phase is where performance is won or lost. You will hold end-to-end ownership of logical
andphysical synthesis, and formal verification, ensuring our chips achieve industry-leading Pow
er,Performance, and Area (PPA) targets while maintaining 100% logical integri

ty.
Key Responsibili
tiesSynthesis & PPA Optimiza
tion● End-to-End Ownership: Define and drive the synthesis strategy, from initial
RTLhandoff through complex gate-level netlist generation and timing clos
ure.● Low-Power Implementation: Drive front-end low-power optimization using
UPF,ensuring sophisticated power-gating and multi-voltage strategies are impleme
ntedflawles
sly.● PPA Leadership: Collaborate closely with RTL, DFT, and Physical Design team
s tosqueeze every bit of performance and area efficiency out of the design during
theRTL-to-Netlist transit
ion.Formal Verification & Sign
-off● Logical Equivalence (LEC): Own the formal verification flow, with hands-on expertis
e inConformal Low Power to ensure functional consistency across synthesis
andlow-power inserti

ons.
● Analysis & Debug: Drive signal integrity (SI) and noise analysis flows to ensure r
obustnetlist quality before handing off to the Physical Design

team.
Key Skills & Technical Requir
ements● Synthesis Mastery: Deep knowledge of both logical and physical synthesis
flows(Topographical/Physical-aware synth
esis).● Tool Proficiency: Expert-level experience with Cadence or Synopsys suites, specif
icallyGenus, DC, Tempus/PrimeTime, and Conf
ormal.● Formal Verification: Proven track record in LEC, specifically handling c
omplexlow-power structures and multi-voltage do
mains.● Timing & SI Expert: Expert-level understanding of MCMM timing closure,
signalintegrity, and the impact of cross-talk on high-speed AI
paths.● Architecture Awareness: Good understanding of scan architecture, DFT mode
s, andPnR methodologies to ensure synthesis is "DFT-friendly" and "Place-frie
ndly."● Scripting: Proficiency in Tcl and Python to automate synthesis and timing an
alysispipe

lines.
Technical Leadership & Bac
kground● Mentorship: Actively mentor junior engineers, establishing best practices for con
straintdevelopment and front-end
flows.● Project Management: Work with the Project Lead to define execution schedules
, trackprogress, and proactively manage technical risks during the tape-out
cycle.● Education: Bachelor’s or Master’s degree in Electrical/Electronics Engineeri
ng or arelated
field.● The Startup Mindset: Ability to build high-quality front-end flows from scratch in
a lean,fast-moving envir
onment.
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