H
Substrait Design engineer
Accepting applicationsHCLTech · Sunnyvale, CA
Full-Time Mid_senior AIASICCadenceCalibreInnovus
Posted
1d ago
Category
Manufacturing
Experience
Mid_senior
Country
United States
HCLTech is looking for a highly talented and self- motivated Substrait Design engineer to join it in advancing the technological world through innovation and creativity.
Job Title: Substrait Design engineer
Job REQ ID: 117930
Position Type: Full Time
Location: Sunnyvale CA (Remote is also okay)
Job Description:
We are seeking a highly skilled and detail-oriented Silicon Substrate Design Engineer to drive the physical design and layout implementation of next-generation 2D, 2.5D and 3D heterogeneous packaging architectures. Specializing in Silicon Interposer and Redistribution Layer (RDL) technologies, you will collaborate closely with ASIC architecture, foundry partners, OSATs, and Signal/Power Integrity (SI/PI) teams to deliver robust, high-density interconnect solutions for high-performance computing (HPC), AI accelerators, and high-speed networking applications.
Key Responsibilities
● Physical Layout & Routing: Own the end-to-end physical design, floor planning, and layout of passive/active silicon interposers and high-density RDL fan-out packages.1
● High-Density Interconnects: Execute complex routing for ultra-fine-pitch microbumps, C4 bumps, TSVs (Through-Silicon Vias), microvias, and pillar structures.1
● Interface Implementation: Route critical high-speed, high-bandwidth interfaces such as HBM, PCIe Gen 5/Gen 6, and die-to-die interfaces with stringent impedance controls.1
● Design Optimization: Actively drive die-package-board co-optimization (DPCO) by mapping bump assignments and floorplans across multiple disparate chiplets.1
● Constraint Implementation: Incorporate layout constraints provided by SI/PI teams, optimizing power delivery networks (PDN) and implementing shielding strategies to minimize crosstalk, insertion loss, and IR drop.1
● Verification: Run and resolve comprehensive physical verification checks, including Design Rule Checks (DRC), Layout Versus Schematic (LVS), connectivity, and antenna rules.1
● DFM & Yield: Collaborate with leading silicon foundries and OSATs to ensure strict alignment
with Design for Manufacturing (DFM), Design for Assembly (DFA), and reliability standards to maximize production yields.1
Required Skills & Qualifications Technical Expertise
● Deep understanding of 2.5D/3D advanced packaging architectures, wafer-level packaging (WLP), and substrate technologies.1
● Mastery of layout routing constraints, stack-up optimization, and silicon processing limits (e.g., fine-line/space lithography down to sub-micron scales for RDL).1
● Solid grasp of electromagnetic and transmission line fundamentals, signal integrity constraints, and thermal-mechanical stress factors in silicon-interposer assemblies.1 Tool & EDA Proficiency
● Extensive hands-on experience with advanced IC packaging and IC layout tools, including:
● Cadence Suite: APD, Allegro Package Designer Plus, Innovus, Virtuoso.1
● Verification: Siemens EDA Calibre, Ansys (HFSS/SIwave for layout review), and IC Validator.1
Soft Skills & Experience
● Excellent cross-functional communication skills, with a proven ability to bridge gaps between silicon design teams and manufacturing foundries.1
● Strong debugging and problem-solving skills when addressing complex DRC violations and multi-die routing bottlenecks.1
Education & Experience Requirements
● Education: Bachelor’s, Master’s, or Ph.D. in Electrical Engineering, Electronics, Microelectronics, Materials Science, or a closely related field.1
● Experience (Engineer): 3+ years of experience in silicon physical design or IC package layout.1
● Experience (Senior/Staff Engineer): 6–10+ years of hands-on experience delivering production-ready 2.5D/3D interposer or high-density fan-out (HDFO) designs from concept to tape-out.
Pay and Benefits
Pay Range Minimum: $92000/annum
Pay Range Maximum: $141000/annum
HCLTech is an equal opportunity employer, committed to providing equal employment opportunities to all applicants and employees regardless of race, religion, sex, color, age, national origin, pregnancy, sexual orientation, physical disability or genetic information, military or veteran status, or any other protected classification, in accordance with federal, state, and/or local law. Should any applicant have concerns about discrimination in the hiring process, they should provide a detailed report of those concerns to secure@hcltech.com for investigation.
A candidate’s pay within the range will depend on their skills, experience, education, and other factors permitted by law. This role may also be eligible for performance-based bonuses subject to company policies. In addition, this role is eligible for the following benefits subject to company policies: medical, dental, vision, pharmacy, life, accidental death & dismemberment, and disability insurance; employee assistance program; 401(k) retirement plan; 10 days of paid time off per year (some positions are eligible for need-based leave with no designated number of leave days per year); and 10 paid holidays per year
How You’ll Grow
At HCLTech, we offer continuous opportunities for you to find your spark and grow with us. We want you to be happy and satisfied with your role and to really learn what type of work sparks your brilliance the best. Throughout your time with us, we offer transparent communication with senior-level employees, learning and career development programs at every level, and opportunities to experiment in different roles or even pivot industries. We believe that you should be in control of your career with unlimited opportunities to find the role that fits you best
you best
Show more Show less
Job Title: Substrait Design engineer
Job REQ ID: 117930
Position Type: Full Time
Location: Sunnyvale CA (Remote is also okay)
Job Description:
We are seeking a highly skilled and detail-oriented Silicon Substrate Design Engineer to drive the physical design and layout implementation of next-generation 2D, 2.5D and 3D heterogeneous packaging architectures. Specializing in Silicon Interposer and Redistribution Layer (RDL) technologies, you will collaborate closely with ASIC architecture, foundry partners, OSATs, and Signal/Power Integrity (SI/PI) teams to deliver robust, high-density interconnect solutions for high-performance computing (HPC), AI accelerators, and high-speed networking applications.
Key Responsibilities
● Physical Layout & Routing: Own the end-to-end physical design, floor planning, and layout of passive/active silicon interposers and high-density RDL fan-out packages.1
● High-Density Interconnects: Execute complex routing for ultra-fine-pitch microbumps, C4 bumps, TSVs (Through-Silicon Vias), microvias, and pillar structures.1
● Interface Implementation: Route critical high-speed, high-bandwidth interfaces such as HBM, PCIe Gen 5/Gen 6, and die-to-die interfaces with stringent impedance controls.1
● Design Optimization: Actively drive die-package-board co-optimization (DPCO) by mapping bump assignments and floorplans across multiple disparate chiplets.1
● Constraint Implementation: Incorporate layout constraints provided by SI/PI teams, optimizing power delivery networks (PDN) and implementing shielding strategies to minimize crosstalk, insertion loss, and IR drop.1
● Verification: Run and resolve comprehensive physical verification checks, including Design Rule Checks (DRC), Layout Versus Schematic (LVS), connectivity, and antenna rules.1
● DFM & Yield: Collaborate with leading silicon foundries and OSATs to ensure strict alignment
with Design for Manufacturing (DFM), Design for Assembly (DFA), and reliability standards to maximize production yields.1
Required Skills & Qualifications Technical Expertise
● Deep understanding of 2.5D/3D advanced packaging architectures, wafer-level packaging (WLP), and substrate technologies.1
● Mastery of layout routing constraints, stack-up optimization, and silicon processing limits (e.g., fine-line/space lithography down to sub-micron scales for RDL).1
● Solid grasp of electromagnetic and transmission line fundamentals, signal integrity constraints, and thermal-mechanical stress factors in silicon-interposer assemblies.1 Tool & EDA Proficiency
● Extensive hands-on experience with advanced IC packaging and IC layout tools, including:
● Cadence Suite: APD, Allegro Package Designer Plus, Innovus, Virtuoso.1
● Verification: Siemens EDA Calibre, Ansys (HFSS/SIwave for layout review), and IC Validator.1
Soft Skills & Experience
● Excellent cross-functional communication skills, with a proven ability to bridge gaps between silicon design teams and manufacturing foundries.1
● Strong debugging and problem-solving skills when addressing complex DRC violations and multi-die routing bottlenecks.1
Education & Experience Requirements
● Education: Bachelor’s, Master’s, or Ph.D. in Electrical Engineering, Electronics, Microelectronics, Materials Science, or a closely related field.1
● Experience (Engineer): 3+ years of experience in silicon physical design or IC package layout.1
● Experience (Senior/Staff Engineer): 6–10+ years of hands-on experience delivering production-ready 2.5D/3D interposer or high-density fan-out (HDFO) designs from concept to tape-out.
Pay and Benefits
Pay Range Minimum: $92000/annum
Pay Range Maximum: $141000/annum
HCLTech is an equal opportunity employer, committed to providing equal employment opportunities to all applicants and employees regardless of race, religion, sex, color, age, national origin, pregnancy, sexual orientation, physical disability or genetic information, military or veteran status, or any other protected classification, in accordance with federal, state, and/or local law. Should any applicant have concerns about discrimination in the hiring process, they should provide a detailed report of those concerns to secure@hcltech.com for investigation.
A candidate’s pay within the range will depend on their skills, experience, education, and other factors permitted by law. This role may also be eligible for performance-based bonuses subject to company policies. In addition, this role is eligible for the following benefits subject to company policies: medical, dental, vision, pharmacy, life, accidental death & dismemberment, and disability insurance; employee assistance program; 401(k) retirement plan; 10 days of paid time off per year (some positions are eligible for need-based leave with no designated number of leave days per year); and 10 paid holidays per year
How You’ll Grow
At HCLTech, we offer continuous opportunities for you to find your spark and grow with us. We want you to be happy and satisfied with your role and to really learn what type of work sparks your brilliance the best. Throughout your time with us, we offer transparent communication with senior-level employees, learning and career development programs at every level, and opportunities to experiment in different roles or even pivot industries. We believe that you should be in control of your career with unlimited opportunities to find the role that fits you best
you best
Show more Show less