OG
Static Timing Analysis (STA) Engineer
Accepting applicationsOho Group · San Jose, CA
Full-Time Mid_senior ASICCadenceGenusRTLSoC
Posted
4d ago
Category
Design
Experience
Mid_senior
Country
United States
A well-funded stealth semiconductor startup building next-generation silicon with an experienced leadership team and ambitious roadmap.
As they grow their engineering organisation, we're looking for an experienced Static Timing Analysis Engineer to play a key role in delivering silicon success.
What You'll Do
Own end-to-end STA and timing signoff for advanced-node ASIC/SoC designs from synthesis through tapeout.
Drive timing closure using PrimeTime and/or Tempus across MCMM scenarios.
Develop and maintain SDC constraints, debug timing violations, and implement timing ECOs.
Partner closely with RTL, synthesis, and physical design teams to optimise timing, power, and area.
Enhance STA methodologies, automation, and signoff flows.
What We're Looking For
10+ years' experience in STA and timing signoff for complex ASIC/SoC designs.
Expert knowledge of Synopsys PrimeTime and/or Cadence Tempus.
Strong experience with SDC development, MCMM analysis, OCV/AOCV/POCV, and advanced-node timing closure (7nm/5nm or below).
Familiarity with Design Compiler and/or Cadence Genus, SI-aware STA, UPF/CPF, and Tcl scripting.
Strong analytical skills with the ability to solve complex timing challenges independently.
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As they grow their engineering organisation, we're looking for an experienced Static Timing Analysis Engineer to play a key role in delivering silicon success.
What You'll Do
Own end-to-end STA and timing signoff for advanced-node ASIC/SoC designs from synthesis through tapeout.
Drive timing closure using PrimeTime and/or Tempus across MCMM scenarios.
Develop and maintain SDC constraints, debug timing violations, and implement timing ECOs.
Partner closely with RTL, synthesis, and physical design teams to optimise timing, power, and area.
Enhance STA methodologies, automation, and signoff flows.
What We're Looking For
10+ years' experience in STA and timing signoff for complex ASIC/SoC designs.
Expert knowledge of Synopsys PrimeTime and/or Cadence Tempus.
Strong experience with SDC development, MCMM analysis, OCV/AOCV/POCV, and advanced-node timing closure (7nm/5nm or below).
Familiarity with Design Compiler and/or Cadence Genus, SI-aware STA, UPF/CPF, and Tcl scripting.
Strong analytical skills with the ability to solve complex timing challenges independently.
Show more Show less