Static Timing Analysis (STA) Engineer

Static Timing Analysis (STA) Engineer
Company: leadIC Design Pvt Ltd
Location: Bengaluru, Karnataka, India
Work Mode: Hybrid
Employment Type: Full-time
About the Role
leadIC Design Pvt Ltd is looking for experienced Static Timing Analysis (STA) Engineers to work on timing analysis, timing closure, and signoff for ASIC/SoC designs.
This role is specifically focused on Static Timing Analysis (STA) and timing signoff. We are looking for candidates with hands-on STA experience rather than general VLSI or Physical Design experience.
Key Responsibilities
Perform Static Timing Analysis (STA) for block-level and/or full-chip ASIC/SoC designs.
Analyze and close setup and hold timing violations.
Perform timing signoff across multiple modes and PVT/RC corners.
Develop, validate, and debug SDC (Synopsys Design Constraints).
Perform MMMC (Multi-Mode Multi-Corner) timing analysis.
Analyze clock latency, clock skew, uncertainty, jitter, and clock paths.
Perform timing analysis using Synopsys PrimeTime and/or Cadence Tempus.
Analyze OCV, AOCV, POCV, LVF, and CRPR/CPPR effects.
Debug timing issues caused by parasitics, routing, crosstalk, and signal integrity.
Perform timing ECOs and work with Physical Design teams for timing closure.
Analyze WNS, TNS, critical paths, path groups, and timing reports.
Work with SPEF, RC corners, extracted parasitics, and signoff libraries.
Develop STA automation and reporting using Tcl/Python/Perl where required.
Required Experience
Hands-on experience specifically in Static Timing Analysis (STA).
Experience in STA signoff and timing closure.
Strong knowledge of setup/hold analysis.
Hands-on experience with PrimeTime and/or Tempus.
Strong understanding of SDC constraints.
Experience with MMMC/MCMM analysis.
Understanding of PVT, RC corners, OCV/AOCV/POCV.
Experience debugging timing violations and performing timing ECOs.
Understanding of clock timing, CTS, skew, latency, and uncertainty.
Knowledge of crosstalk/SI and parasitic effects.
Preferred Profile
We are particularly interested in candidates whose current or previous role includes titles such as:
STA Engineer
Static Timing Analysis Engineer
STA Signoff Engineer
Timing Signoff Engineer
Senior STA Engineer
STA Lead
Timing Analysis Engineer
Candidates should have actual project experience in STA/timing signoff, not only general Physical Design, RTL, Synthesis, or DFT.
Important: Who Should Apply?
Please apply if you have hands-on experience in Static Timing Analysis (STA), timing closure, or timing signoff.
Candidates with only general Physical Design, RTL Design, Verification, DFT, or Synthesis experience without hands-on STA experience may not be suitable for this position.
Education
Bachelor's/Master's degree in Electrical Engineering, Electronics, VLSI, Microelectronics, or a related discipline.
Experience
Relevant STA experience is required.
Experience level can be considered based on the candidate's depth of hands-on STA/signoff and timing closure experience.
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