Standard Cell Layout Engineer - 4+ Years - Bangalore Location

Company Description LeadIC Design is a fast-growing VLSI engineering company founded in 2018, focused on accelerating semiconductor innovation for global product and IP teams. The company supports the complete chip development lifecycle, from circuits and layout to digital design, physical design, and verification. With engineering teams across India and Canada, LeadIC delivers high-quality, partnership-driven design services tailored to product-focused semiconductor organizations. The culture emphasizes strong technical ownership, predictable delivery, and rigorous quality practices. LeadIC is a trusted long-term partner for leading semiconductor companies seeking scalable, high-performing engineering teams.
Role Description This is a full-time, on-site Standard Cell Layout Engineer role based in Bengaluru. The engineer will be responsible for designing and optimizing standard cell layouts to meet performance, area, power, and reliability targets across advanced technology nodes. Day-to-day work includes translating circuit schematics into robust layout, running and debugging DRC/LVS checks, and collaborating with circuit design, physical design, and verification teams to close design issues. The role involves maintaining layout quality and consistency across libraries, adhering to foundry design rules, and contributing to layout automation or methodology improvements where relevant. The engineer will also participate in design reviews, documentation, and continuous enhancement of layout best practices within the team.
Qualifications
Strong proficiency in Layout Design for standard cells, including floorplanning, device placement, routing, and optimization.
Solid understanding of Circuit Design concepts, with the ability to interpret schematics and translate them into manufacturable layouts.
Hands-on experience with Analog and Analog Circuits fundamentals relevant to layout constraints, matching, parasitics, and reliability.
Practical experience with Physical Verification flows such as DRC, LVS, and related signoff checks.
Proficiency with industry-standard EDA tools for layout and verification (e.g., Cadence Virtuoso, Synopsys, Mentor/Siemens tools).
Good knowledge of CMOS process, design rules, and advanced technology node considerations.
Bachelor’s or Master’s degree in Electronics, Electrical Engineering, VLSI, or a related discipline.
4+ years of relevant experience in standard cell or custom layout, preferably in semiconductor product or services companies.
Strong analytical skills, attention to detail, and ability to collaborate effectively with cross-functional engineering teams.
Ability to work independently, manage priorities in a fast-paced environment, and uphold high quality standards.
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