Standard Cell Design Engineer – ASIC Library Development

Standard Cell Design Engineer ASIC Library Development

Location: Bengaluru, India
Work Mode: Onsite
Experience: 5- 12 Years
Industry: Semiconductor / VLSI / ASIC Design

Role Overview

We are seeking a highly skilled Standard Cell Design Engineer to contribute to the development, characterization, validation, and optimization of high-performance standard cell libraries for advanced semiconductor technologies. The role involves designing digital standard cells, optimizing Power, Performance, and Area (PPA), supporting technology enablement, and collaborating with process technology, CAD, physical design, EDA, and product engineering teams to deliver production-ready library solutions for next-generation SoC and ASIC designs.
The ideal candidate will have strong expertise in standard cell architecture, transistor-level CMOS design, characterization, timing validation, and advanced technology nodes.
Key Responsibilities
Design, develop, and optimize digital standard cells for advanced semiconductor process technologies.
Develop high-performance, low-power, and area-efficient standard cell libraries for ASIC and SoC platforms.
Perform transistor-level CMOS circuit design, simulation, optimization, and validation.
Characterize timing, power, noise, and reliability parameters using industry-standard characterization flows.
Develop and validate Liberty (.lib), LEF, GDSII, SPICE, CDL, and timing models.
Collaborate with Process Integration, Device Engineering, CAD, Physical Design, and EDA teams to improve library quality and manufacturability.
Perform layout design review and support DRC, LVS, ERC, antenna, and EM verification.
Optimize libraries for Power, Performance, and Area (PPA) across multiple process corners.
Support new technology bring-up, process migration, silicon correlation, and customer enablement.
Develop automation scripts and methodologies to improve library generation and characterization efficiency.
Investigate silicon correlation issues and drive continuous improvement initiatives.
Support customer design teams during implementation, timing closure, and library deployment.
Required Qualifications
Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, Computer Engineering, or related discipline.
5- 12 years of experience in Standard Cell Library Design, Library Development, or Digital Library Engineering.
Strong understanding of CMOS transistor-level circuit design and semiconductor device behavior.
Experience supporting advanced ASIC or SoC development programs.
Technical Skills Library Development
Standard Cell Design
Digital Library Development
Standard Cell Architecture
Library Characterization
Library Validation
Cell Optimization
Custom Cell Design
Circuit Design
CMOS Circuit Design
Transistor-Level Design
SPICE Simulation
Noise Analysis
Power Optimization
Timing Optimization
Leakage Reduction
Characterization
Liberty (.lib)
LEF
GDSII
CDL
Timing Models
Noise Models
CCS/ECSM Models
PVT Characterization
Physical Verification
DRC
LVS
ERC
Antenna Verification
EMIR Analysis
Layout Review
EDA Tools
Cadence Virtuoso
Synopsys Custom Compiler
Liberate
SiliconSmart
PrimeTime
Calibre
StarRC
Spectre
HSPICE
Programming & Automation
Tcl
Perl
Python
Shell Scripting


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