Staff Verification Engineer, DesignWare IP- High-Speed Protocols/PCIe

Alternate Job Titles

Staff Verification Engineer, DesignWare IP- High-Speed Protocols/PCIe

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years building verification environments that have to actually catch the bugs that matter, not just hit coverage numbers. The difference between IP that ships and IP that gets pulled back is often a corner case you thought to test in week three, and you are the kind of engineer who builds that test before anyone asks for it.

You are comfortable moving between System Verilog testbenches, UVM architecture decisions, and protocol-level debugging without losing sight of what you are actually proving. PCIe is not just a spec to you, it is a set of real-world failure modes you have seen, debugged, and prevented from happening again. You do not wait for a complete test plan to start building, you work with what the RTL team has today, ask the right questions about what is coming next week, and structure your environment so it does not break when requirements shift.

At Synopsys, you will work on DesignWare IP that powers connectivity in everything from data centers to automotive systems. The team is global, the protocols are real, and what you verify will ship.

What You'll Be Doing

Design and implement System Verilog verification environments for DesignWare IP cores, including testbench architecture, stimulus generation, checkers, and coverage models
Develop and execute test plans for PCIe and other high-speed connectivity protocols, covering unit-level and full system integration scenarios
Build and debug complex test cases using UVM, ensuring functional correctness and protocol compliance
Drive functional coverage closure and manage regression suites using VCS, NC, or MTI
Collaborate with RTL designers to reproduce, root-cause, and resolve design issues with clear verification metrics
Automate verification flows using Python, Perl, or TCL to improve efficiency and turnaround time

The Impact You Will Have

Deliver verified, production-quality IP cores that enable connectivity in commercial, enterprise, and automotive systems worldwide
Catch critical design issues early, reducing respins, customer escalations, and time to market
Set the standard for verification quality and coverage rigor across the DesignWare IP portfolio
Mentor junior verification engineers and share best practices that elevate team capability
Enable global R&D teams to move faster by building reusable verification components and infrastructure
Contribute to the success of next-generation connectivity protocols that power the systems our customers are building today

What You'll Need

Bachelor's in Electrical or Electronics Engineering with 5+ years of verification experience, or Master's with 3+ years in ASIC or IP verification
Strong hands-on experience developing System Verilog-based verification environments and testbenches from scratch
Proficiency with UVM, OVM, or VMM methodologies and functional coverage-driven verification
Solid understanding of PCIe protocol and architecture, experience with MIPI-I3C, UFS, AMBA, Ethernet, DDR, or USB is a strong plus
Experience using industry-standard simulators such as VCS, NC, or MTI
Working knowledge of scripting languages like Python, Perl, or TCL for automation

Who You Are

You can take a failing regression, isolate the root cause across thousands of lines of log, and explain the issue to an RTL engineer in two sentences
You write testbenches that other engineers can actually extend six months later without reverse-engineering your intent
You push back when a test plan glosses over a tricky protocol edge case, and you do it in a way that makes the team better
You stay organized across multiple verification tasks and multi-site collaboration without dropping threads
You take initiative when you see a gap in coverage or an inefficient flow, and you fix it before it becomes someone else's problem

The Team You'll Be Part Of

You will join the Solutions Group's DesignWare IP Verification R&D team, a highly skilled and diverse group of engineers dedicated to delivering world-class IP cores for next-generation connectivity. The team operates in a collaborative, multi-site environment, leveraging global expertise to solve complex verification challenges. Together, you will drive innovation, share knowledge, and uphold Synopsys' reputation for technical leadership and excellence.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
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