Staff RTL Engineer

Staff RTL Design Engineer - California - $250k +

A next-level GPU startup are on the lookout for an RTL Design Engineer to join a team developing next-generation complex semiconductor products. This role offers the opportunity to work on challenging digital design projects, collaborating with architecture, verification, and implementation teams throughout the development lifecycle.

Key Responsibilities
Design and implement RTL for complex digital systems using Verilog/SystemVerilog.
Develop high-performance SoC subsystems, interconnects, and memory-related components.
Translate architectural specifications into high-quality, synthesizable RTL.
Optimise designs for performance, power, and area.
Support verification activities through debug, issue resolution, and design reviews.
Collaborate with implementation teams to support timing closure and design integration.
Participate in technical discussions, code reviews, and system-level design activities.
Support silicon bring-up and debug activities when required.

Skills & Experience
10+ years of ASIC or SoC design experience.
Strong RTL design expertise using Verilog and/or SystemVerilog.
Experience developing complex digital systems and SoC components.
Understanding of industry-standard on-chip communication protocols and subsystem integration.
Strong knowledge of pipelining, arbitration, memory systems, and high-performance digital design techniques.
Familiarity with synthesis, timing analysis, and low-power design methodologies.
Experience using leading semiconductor EDA tool flows.
Excellent debugging, analytical, and problem-solving skills.


This is an excellent opportunity for a senior engineer looking to contribute to complex silicon development within a collaborative and technically challenging environment.
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