Staff RTL Design Engineer

A San Jose based Series A start-up are looking for Senior/Staff level RTL Design Engineer to design and implement RTL for complex ASIC/SoC subsystems using SystemVerilog/Verilog.

We are looking for someone to Architect and implement high-performance interconnect fabrics using NoC and AMBA bus systems (AXI/AHB/APB) and memory subsystems.

Required Qualifications

Lead ASIC Front-End Engineer with 10+ years of experience delivering complex silicon from architecture to RTL.
Architected and designed high-performance SoC subsystems and advanced interconnect architectures.
Expert-level RTL development utilizing Verilog and SystemVerilog for large-scale, production-grade designs.
Deep technical expertise in AMBA protocols, successfully implementing AXI, AHB, and APB interfaces in high-throughput environments.
Spearheaded the design and integration of scalable Network-on-Chip (NoC) and custom bus fabrics to optimize on-chip communication.

The work is challenging but rewarding. This is a role for engineers who want to learn, develop and push themselves. Equity offered.
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