Staff Physical Design Engineer (Top-Level EMIR Signoff)

We are seeking a highly experienced Senior/Staff Physical Design Engineer specializing in Top-Level EMIR and Power Integrity Signoff for advanced-node SoC designs (5nm / 3nm / 2nm).
The ideal candidate will have proven expertise in full-chip Static & Dynamic IR Drop analysis, Electromigration verification, PDN optimization, and power integrity closure across multiple successful tapeouts.
You will work closely with RTL, Physical Design, STA, Packaging, and Foundry teams to drive power signoff readiness for high-performance silicon programs.
Key Responsibilities
Drive top-level EMIR signoff for complex SoC designs.
Perform full-chip Static & Dynamic IR Drop analysis.
Execute Electromigration (EM) verification and closure.
Optimize Power Delivery Network (PDN) for reliability and noise margins.
Analyze voltage droop and high-frequency switching behavior.
Debug power integrity issues and drive closure independently.
Collaborate with STA and Physical Design teams to improve PPA and signoff convergence.
Develop scalable methodologies to improve runtime and signoff quality.
Present power integrity risks, status, and mitigation plans to leadership teams.
Required Technical Skills
EMIR / Power Integrity
Static IR Drop
Dynamic IR Drop
Electromigration (EM)
Voltage Droop Analysis
Power Integrity Signoff
Current Density Analysis
PDN Optimization
Tools
Ansys RedHawk-SC
Cadence Voltus
Equivalent EMIR tools
Advanced Node Experience
5nm
3nm
2nm
Additional Skills
Tcl / Python / Perl scripting
Understanding of OCV / AOCV / POCV
Statistical timing methodologies
Full-chip signoff methodologies
Preferred Qualifications
Experience with 2.5D / 3D IC packaging signoff
Familiarity with TSMC / Samsung / Intel signoff flows
Experience in HPC, AI Accelerator, or large-scale SoC programs
Strong debugging and analytical skills
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