Staff Engineer - RTL Design

Master/Bachelor's Degree in Electrical/Electronic Engineering
Experience 8-12 Years in high performance digital logic designs and SoC Integration using ARM Cores, Bus Protocols and Interconnects
Building Subsystems and/or SoC RTL integration
LINT/CDC/RDC signoffs for the highest design quality
Perform all aspects of the SoC design flow from high level design to Synthesis
Experience with Synopsys VCS or Cadence RTL simulator, Design Complier (DC) or RTL Compiler (RC or Genus), Verdi Debugging tool
ISO26262 based functional safety relevant microcontroller architectures is preferred
Conducting IP Integration reviews, BE reports reviews for concurrent engineering
Self-motivated to drive issues to closure.
Excellent written and verbal communication skill
Creative problem-solving skills, logic analysis skills, ability to logically break complex problems down to manageable components,

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