JV
Staff Engineer
Accepting applicationsJobs via Dice · San Jose, CA
Full-Time Senior AIInnovusPerlPythonRTL
Posted
1d ago
Category
Design
Experience
Senior
Country
United States
Dice is the leading career destination for tech experts at every stage of their careers. Our client, Violet Ink, is seeking the following. Apply via Dice today!
Position: Physical Design Engineer / Staff Engineer
Location : San Jose CA
Contract More than 12 months
Relocation consultants are also considerable..
Job Responsibilities:
We are seeking experienced Physical Design Engineers with expertise in top-level signoff for complex SoCs on advanced nodes (7nm/5nm/3nm). Candidates should have multiple full-cycle tapeouts and strong experience in signoff-to-tapeout closure.
Key Responsibilities:
Drive full-chip/top-level signoff activities
Collaborate with RTL, PD, STA, EMIR, and Foundry teams
Resolve timing, power, clocking, and reliability challenges
Improve PPA and signoff turnaround time
Support independent tapeout closure
Specialized Expertise in One or More Areas:
EMIR / Power Integrity (RedHawk-SC, Voltus)
Timing & STA (PrimeTime/PT-SI, Tempus, MMMC)
Clock Distribution / CTS (Innovus, ICC2, H-Tree, Mesh)
Requirements:
8+ years in Physical Design / Signoff
Hands-on experience with 7nm/5nm/3nm tapeouts
Strong knowledge of OCV, AOCV/POCV, STA methodologies
Scripting skills in Tcl/Python/Perl
Experience with HPC, AI accelerators, or large-scale SoCs preferred
Exposure to TSMC/Samsung/Intel signoff methodologies is a plus
Show more Show less
Position: Physical Design Engineer / Staff Engineer
Location : San Jose CA
Contract More than 12 months
Relocation consultants are also considerable..
Job Responsibilities:
We are seeking experienced Physical Design Engineers with expertise in top-level signoff for complex SoCs on advanced nodes (7nm/5nm/3nm). Candidates should have multiple full-cycle tapeouts and strong experience in signoff-to-tapeout closure.
Key Responsibilities:
Drive full-chip/top-level signoff activities
Collaborate with RTL, PD, STA, EMIR, and Foundry teams
Resolve timing, power, clocking, and reliability challenges
Improve PPA and signoff turnaround time
Support independent tapeout closure
Specialized Expertise in One or More Areas:
EMIR / Power Integrity (RedHawk-SC, Voltus)
Timing & STA (PrimeTime/PT-SI, Tempus, MMMC)
Clock Distribution / CTS (Innovus, ICC2, H-Tree, Mesh)
Requirements:
8+ years in Physical Design / Signoff
Hands-on experience with 7nm/5nm/3nm tapeouts
Strong knowledge of OCV, AOCV/POCV, STA methodologies
Scripting skills in Tcl/Python/Perl
Experience with HPC, AI accelerators, or large-scale SoCs preferred
Exposure to TSMC/Samsung/Intel signoff methodologies is a plus
Show more Show less