CT
Staff Design Verification Engineer
Accepting applicationsChiplogic Technologies · Bengaluru, Karnataka, India
Full-Time Mid_senior SystemVerilogUVM
Estimated market salary
₹20-37 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
19h ago
Category
Verification
Experience
Mid_senior
Country
India
Company Description Chiplogic Technologies is an IP and product engineering services company founded in 2018, specializing in Semiconductor, Systems, IoT, and AI/ML solutions. The organization focuses on delivering high-quality, dependable engineering services across the full semiconductor design lifecycle. Chiplogic provides offshore development centers (ODC) and full turnkey semiconductor design and system solutions from concept to silicon. The company also delivers proof-of-concept (POC) and IoT system solutions, leveraging its proprietary VISARD™ (Video Synthesis And Real-time Dynamics) framework. Team members collaborate on cutting-edge technologies and end-to-end product development for global customers.
Role Description The Staff Design Verification Engineer is a full-time, on-site role based in Bengaluru. This role involves planning, developing, and executing verification strategies for complex SoC and IP designs, including testbench architecture, test cases, and coverage models. The engineer will perform functional and formal verification, run simulations, analyze results, and systematically debug RTL and testbench issues in collaboration with design and architecture teams. Daily responsibilities include reviewing specifications, participating in design and verification reviews, refining verification environments, and ensuring verification closure with robust coverage metrics. The role also includes mentoring junior team members, contributing to verification methodology improvements, and supporting tape-out readiness activities.
Job Description:
Participate in the functional verification of a block(s) of complex ASICs and/or IP cores for a combined CPU/GPU development effort.
Be part of a team of design and verification engineers, working closely with other team members to understand and verify the functionality of a given design element within the context of the block, chip and overall system.
Be responsible for carefully documenting and executing test plan(s) consisting of directed and constrained-random tests to be run during simulation.
Be expected to adopt the evolving verification methodologies used in the industry to functionally verify increasingly more complex SoC designs within aggressive, market-driven schedules, and work within the existing verification infrastructure on currently active projects.
Be familiar with hardware modeling and/or assertion-based verification methods.
EXPERIENCE AND EDUCATION:
8-10 years of proven verification experience on large ASIC development projects or software/firmware experience in a hardware development setting
Strong background in C/C++ development in a Linux Environment
Strong debug skills and experience with debug tools such as Gdb, Valgrind
Proficient in Object Oriented programming, STL, computer architecture and data structures
Knowledge of Perl and Make-files
Experience in Verilog/System Verilog/System C, preferred
Experience in C/Verilog environment using DPI/PLI, preferred
Strong analytical skills and attention to detail
Excellent written and communication skills
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Role Description The Staff Design Verification Engineer is a full-time, on-site role based in Bengaluru. This role involves planning, developing, and executing verification strategies for complex SoC and IP designs, including testbench architecture, test cases, and coverage models. The engineer will perform functional and formal verification, run simulations, analyze results, and systematically debug RTL and testbench issues in collaboration with design and architecture teams. Daily responsibilities include reviewing specifications, participating in design and verification reviews, refining verification environments, and ensuring verification closure with robust coverage metrics. The role also includes mentoring junior team members, contributing to verification methodology improvements, and supporting tape-out readiness activities.
Job Description:
Participate in the functional verification of a block(s) of complex ASICs and/or IP cores for a combined CPU/GPU development effort.
Be part of a team of design and verification engineers, working closely with other team members to understand and verify the functionality of a given design element within the context of the block, chip and overall system.
Be responsible for carefully documenting and executing test plan(s) consisting of directed and constrained-random tests to be run during simulation.
Be expected to adopt the evolving verification methodologies used in the industry to functionally verify increasingly more complex SoC designs within aggressive, market-driven schedules, and work within the existing verification infrastructure on currently active projects.
Be familiar with hardware modeling and/or assertion-based verification methods.
EXPERIENCE AND EDUCATION:
8-10 years of proven verification experience on large ASIC development projects or software/firmware experience in a hardware development setting
Strong background in C/C++ development in a Linux Environment
Strong debug skills and experience with debug tools such as Gdb, Valgrind
Proficient in Object Oriented programming, STL, computer architecture and data structures
Knowledge of Perl and Make-files
Experience in Verilog/System Verilog/System C, preferred
Experience in C/Verilog environment using DPI/PLI, preferred
Strong analytical skills and attention to detail
Excellent written and communication skills
Show more Show less