Staff Design Verification

Key Responsibilities

• Develop and execute verification plans based on design specifications
• Create testbenches using SystemVerilog, UVM, or similar methodologies
• Write test cases to validate functionality, performance, and corner cases
• Perform functional and code coverage analysis
• Debug design issues and collaborate with design engineers to resolve bugs
• Use simulation tools (e.g., VCS, ModelSim, Xcelium) to run tests
• Develop reusable verification components and environments
• Conduct regression testing and ensure design stability
• Document verification results and provide detailed reports

Required Skills & Qualifications

• Bachelor’s/Master’s degree in Electronics, Electrical Engineering, or related field
• Strong knowledge of digital design fundamentals
• Experience with HDL languages (Verilog/SystemVerilog)
• Familiarity with UVM (Universal Verification Methodology)
• Understanding of simulation and debugging tools
• Knowledge of scripting languages (Python, Perl, or Shell)
• Good problem-solving and analytical skills

Preferred Skills

• Experience with ASIC/SoC verification
• Knowledge of formal verification techniques
• Familiarity with protocols (AXI, PCIe, USB, Ethernet, etc.)
• Exposure to coverage-driven verification
• Experience with emulation or FPGA prototyping