IR
Staff Analog IC Design Engineer
Accepting applicationsIC Resources · San Francisco Bay Area
Full-Time Mid_senior AnalogCMOSCadenceaianalog
Posted
24 Apr
Category
Design
Experience
Mid_senior
Country
United States
Staff Analog IC Design Engineer – High-Speed Custom Logic (Hybrid) | Permanent | Deep Tech Client
We're working with a well-funded deep tech company building next-generation computing hardware at the edge of what silicon can do. This is genuine frontier work, not incremental improvement on existing architectures.
They're looking for a Staff-level analog IC designer who has operated at the performance limits of advanced CMOS nodes. If you've taped out domino or dynamic logic in sub-45nm and you know what it takes to close timing on ultra-deep pipelines, this role was written for you.
What you'll be doing:
Architecting and designing high-speed custom logic blocks — adders, shift registers, modular arithmetic units. Optimizing domino logic paths for maximum speed including keeper strategies, clock skew management and charge sharing. Conducting PVT corner analysis, Monte Carlo simulation and parasitic extraction. Collaborating with layout engineers on parasitic-aware optimization and layout-dependent effects. Supporting silicon bring-up and correlating simulation against measured silicon data.
What you need:
8 to 10 years in analog or custom IC design. Proven domino or dynamic logic tape-outs in 45nm or below. Strong device physics background including threshold voltage, body biasing, device stacking and interconnect RC effects. Cadence Virtuoso, Spectre/APS, Quantus or StarRC. MEng, MSc or PhD in Electronic or Electrical Engineering.
This is a rare role in a genuinely differentiated technology space. The work is technically demanding and the team is senior. If you're the kind of engineer who finds process-limit design problems interesting rather than stressful, get in touch.
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We're working with a well-funded deep tech company building next-generation computing hardware at the edge of what silicon can do. This is genuine frontier work, not incremental improvement on existing architectures.
They're looking for a Staff-level analog IC designer who has operated at the performance limits of advanced CMOS nodes. If you've taped out domino or dynamic logic in sub-45nm and you know what it takes to close timing on ultra-deep pipelines, this role was written for you.
What you'll be doing:
Architecting and designing high-speed custom logic blocks — adders, shift registers, modular arithmetic units. Optimizing domino logic paths for maximum speed including keeper strategies, clock skew management and charge sharing. Conducting PVT corner analysis, Monte Carlo simulation and parasitic extraction. Collaborating with layout engineers on parasitic-aware optimization and layout-dependent effects. Supporting silicon bring-up and correlating simulation against measured silicon data.
What you need:
8 to 10 years in analog or custom IC design. Proven domino or dynamic logic tape-outs in 45nm or below. Strong device physics background including threshold voltage, body biasing, device stacking and interconnect RC effects. Cadence Virtuoso, Spectre/APS, Quantus or StarRC. MEng, MSc or PhD in Electronic or Electrical Engineering.
This is a rare role in a genuinely differentiated technology space. The work is technically demanding and the team is senior. If you're the kind of engineer who finds process-limit design problems interesting rather than stressful, get in touch.
Show more Show less