MT
STA/RTL engineer
Accepting applicationsMirafra Technologies · California, United States
Full-Time Mid_senior CadenceDFTRTLSynopsysmentor
Posted
3d ago
Category
Design
Experience
Mid_senior
Country
United States
Your Impact
You are a diligent Design/SDC Engineer with strong analytical skills and a deep understanding of timing constraints, including clock groups, exceptions, and clock exclusivity. Proficient in industry-standard SDC/STA tools and scripting for automation, you excel at identifying and resolving timing issues across all design levels. You will collaborate with Front-end and Back-end teams to understand chip architecture and guide them in refining design and timing constraints for seamless physical design closure. As part of this team, you’ll contribute to developing next-generation networking chips.
Responsibilities include:
Being a member of design team who oversees fullchip SDCs and works with physical design and DFT teams to close fullchip timing in multiple timing modes.
Helping develop efficient methodology to promote block level SDCs to fullchip, and to bring fullchip SDC changes back to block level.
Helping develop and apply methodology to ensure correctness and quality of SDCs as early as possible in design cycle.
Reviewing block level SDCs and clocking diagrams and mentor other RTL design owners on SDC development.
Leading the fullchip clocking design including diagrams and related documentation.
Preferred Qualifications:
Experience in Static Timing Analysis.
Experience with constraint analyzer tools such as Fishtail/TCM (Timing Constraint Manager from Synopsys) and CCD (Conformal Constraint Designer from Cadence).
Experience with Spyglass CDC and glitch analysis.
Experience with STA tools such as PrimeTime/Tempus.
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You are a diligent Design/SDC Engineer with strong analytical skills and a deep understanding of timing constraints, including clock groups, exceptions, and clock exclusivity. Proficient in industry-standard SDC/STA tools and scripting for automation, you excel at identifying and resolving timing issues across all design levels. You will collaborate with Front-end and Back-end teams to understand chip architecture and guide them in refining design and timing constraints for seamless physical design closure. As part of this team, you’ll contribute to developing next-generation networking chips.
Responsibilities include:
Being a member of design team who oversees fullchip SDCs and works with physical design and DFT teams to close fullchip timing in multiple timing modes.
Helping develop efficient methodology to promote block level SDCs to fullchip, and to bring fullchip SDC changes back to block level.
Helping develop and apply methodology to ensure correctness and quality of SDCs as early as possible in design cycle.
Reviewing block level SDCs and clocking diagrams and mentor other RTL design owners on SDC development.
Leading the fullchip clocking design including diagrams and related documentation.
Preferred Qualifications:
Experience in Static Timing Analysis.
Experience with constraint analyzer tools such as Fishtail/TCM (Timing Constraint Manager from Synopsys) and CCD (Conformal Constraint Designer from Cadence).
Experience with Spyglass CDC and glitch analysis.
Experience with STA tools such as PrimeTime/Tempus.
Show more Show less