STA Lead

STA Lead
Location: Bengaluru, India
Experience: 6–10 Years
Role Overview
We are seeking a highly skilled STA Lead to drive timing closure and signoff for complex SoC, CPU, AI/ML, and high-performance computing designs at advanced technology nodes. This is a hands-on technical role focused on timing analysis, signoff quality, methodology development, and achieving first-pass silicon success.
Key Responsibilities
Own block and subsystem-level STA closure from synthesis through signoff.
Drive timing budgeting, constraints development, MCMM analysis, and timing convergence.
Analyze and resolve setup/hold, OCV/AOCV/POCV, CRPR, crosstalk, CDC, and timing ECO challenges.
Collaborate closely with RTL, synthesis, physical design, CTS, SI, and signoff teams to achieve timing closure.
Support timing signoff reviews and tapeout readiness activities.
Develop automation and productivity improvements using scripting.
Required Skills & Qualifications
B.E./B.Tech/M.E./M.Tech in Electronics, Electrical Engineering, VLSI, or related fields.
6–10 years of experience in STA, timing closure, and signoff for advanced-node SoC designs.
Strong expertise in:
Static Timing Analysis (STA)
MCMM Timing Closure
OCV/AOCV/POCV, CRPR
SDC Constraints Development & Validation
Crosstalk and Noise Analysis
Clock Architecture and CTS
Timing ECO Methodologies
RTL-to-GDSII Implementation Flow
Hands-on experience with PrimeTime, Tempus, Fusion Compiler, Innovus, and Tcl/Python/Perl scripting.
Experience with CPU, GPU, AI Accelerator, Networking, or High-Performance SoC designs is highly desirable.
Proven track record of driving timing closure and supporting successful tapeouts.
Preferred
Experience mentoring junior engineers and leading timing closure activities.
Strong debugging, analytical, and problem-solving skills.
Exposure to advanced technology nodes (7nm/5nm/3nm) and silicon correlation activities.
Join us to solve challenging timing problems and enable the next generation of high-performance semiconductor products.
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