EI
STA Engineer ( Physical Design Engineer )
Accepting applicationsExtend Information Systems Inc. · San Jose, CA
Contract Mid_senior CadenceCalibreSynopsys
Posted
22h ago
Category
Design
Experience
Mid_senior
Country
United States
STA Engineer ( Physical Design Engineer )
San Jose, CA
Responsibilities:
Own full-chip clocking across all PVT corners and modes.
Manage MMMC (Multi-Mode Multi-Corner) timing closure.
Handle timing constraints and hierarchical budgeting.
Drive functional and timing ECO closure.
Achieve final timing signoff for tapeout.
Tools
Synopsys PrimeTime (PT/PT-SI)
Cadence Tempus
Minimum Qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, or equivalent practical experience.
15+ years of hands-on experience in physical Verification in Top level.
Proficiency in utilizing Electronic Design Automation (EDA) tools such as Peagasus and Calibre.
Show more Show less
San Jose, CA
Responsibilities:
Own full-chip clocking across all PVT corners and modes.
Manage MMMC (Multi-Mode Multi-Corner) timing closure.
Handle timing constraints and hierarchical budgeting.
Drive functional and timing ECO closure.
Achieve final timing signoff for tapeout.
Tools
Synopsys PrimeTime (PT/PT-SI)
Cadence Tempus
Minimum Qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, or equivalent practical experience.
15+ years of hands-on experience in physical Verification in Top level.
Proficiency in utilizing Electronic Design Automation (EDA) tools such as Peagasus and Calibre.
Show more Show less
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