STA Engineer

• Work closely with design teams to understand the requirements and constraints of the design.
• Write and implement block level and top-level constraints for synthesis and STA.
• Experience of performing STA preferably with both Tempus and Primetime
• STA and Timing closure using MMMC in both functional and DFT modes
• Experience on SDF generation and validation and support to functional verification team during GLS.
• ETM /timing model generation and validation at IP level.
• Working in partnership with SoC teams to support the IP at SoC level.


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