MT

STA Engineer

Accepting applications

Mirafra Technologies · Austin, TX

Full-Time Mid_senior ASICPerlPythonTcl
Posted
6d ago
Category
Design
Experience
Mid_senior
Country
United States
6+ years of experience with a Bachelor’s Degree in Computer Science/Engineering, or 4+ years of experience with a Master’s Degree, or 2+ years of experience with a Ph.D.
Solid understanding and hands-on experience with ASIC design flows and electrical engineering fundamentals.
Working knowledge and experience with POCV, derating methodologies, and timing analysis.
Strong hands-on experience with industry-standard STA tools (e.g. PrimeTime, Tempus).
Solid hands-on experience with clock tree synthesis (CTS), multi-voltage and multi-clock designs.
Working knowledge of formal equivalency checks, low-power checks, timing constraints, UPF.
Strong scripting /programming skills in Tcl, Perl, Shell, and/or Python.

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