LT
STA Engineer
Accepting applicationsLeadSoc Technologies Pvt Ltd · Bengaluru, Karnataka, India
Full-Time Mid_senior DFTRTLSoCSynopsysTCL
Posted
3d ago
Category
Design
Experience
Mid_senior
Country
India
Here's a professional STA Engineer Job Post suitable for LinkedIn and job portals.
🚀 Hiring: Static Timing Analysis (STA) Engineer
📍 Location: Bengaluru
💼 Experience: 3–7 Years
⏳ Notice Period: Immediate to 30 Days Preferred
Key Responsibilities
Perform block-level and full-chip Static Timing Analysis (STA).
Develop and validate timing constraints (SDC) for complex SoC designs.
Analyze and debug setup, hold, recovery, removal, and clock gating timing violations.
Perform timing sign-off across multiple PVT corners and operating modes.
Work on multi-mode, multi-corner (MMMC) timing analysis and closure.
Collaborate with RTL, Synthesis, Physical Design, CTS, DFT, and ECO teams to achieve timing closure.
Analyze timing reports and optimize timing, power, and area.
Support ECO implementation and timing verification.
Develop automation scripts using TCL for STA flow and reporting.
Required Skills
Strong experience in Static Timing Analysis (STA) and timing sign-off.
Hands-on experience with Synopsys PrimeTime (mandatory).
Good understanding of timing constraints (SDC), MMMC, OCV/AOCV/POCV, and timing exceptions.
Experience in setup/hold analysis, clock tree analysis, and timing closure.
Knowledge of synthesis and physical design flow.
Familiarity with advanced technology nodes (16nm/7nm/5nm/3nm) is preferred.
Strong TCL scripting skills for automation.
Excellent debugging, analytical, and problem-solving skills.
Good communication skills and ability to work effectively with cross-functional teams.
Education
Bachelor's or Master's degree in Electronics & Communication Engineering (ECE), Electrical Engineering (EEE), Electronics & Instrumentation (E&I), VLSI Design, Microelectronics, or a related field.
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🚀 Hiring: Static Timing Analysis (STA) Engineer
📍 Location: Bengaluru
💼 Experience: 3–7 Years
⏳ Notice Period: Immediate to 30 Days Preferred
Key Responsibilities
Perform block-level and full-chip Static Timing Analysis (STA).
Develop and validate timing constraints (SDC) for complex SoC designs.
Analyze and debug setup, hold, recovery, removal, and clock gating timing violations.
Perform timing sign-off across multiple PVT corners and operating modes.
Work on multi-mode, multi-corner (MMMC) timing analysis and closure.
Collaborate with RTL, Synthesis, Physical Design, CTS, DFT, and ECO teams to achieve timing closure.
Analyze timing reports and optimize timing, power, and area.
Support ECO implementation and timing verification.
Develop automation scripts using TCL for STA flow and reporting.
Required Skills
Strong experience in Static Timing Analysis (STA) and timing sign-off.
Hands-on experience with Synopsys PrimeTime (mandatory).
Good understanding of timing constraints (SDC), MMMC, OCV/AOCV/POCV, and timing exceptions.
Experience in setup/hold analysis, clock tree analysis, and timing closure.
Knowledge of synthesis and physical design flow.
Familiarity with advanced technology nodes (16nm/7nm/5nm/3nm) is preferred.
Strong TCL scripting skills for automation.
Excellent debugging, analytical, and problem-solving skills.
Good communication skills and ability to work effectively with cross-functional teams.
Education
Bachelor's or Master's degree in Electronics & Communication Engineering (ECE), Electrical Engineering (EEE), Electronics & Instrumentation (E&I), VLSI Design, Microelectronics, or a related field.
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