LD
STA Engineer
Accepting applicationsleadIC Design Pvt Ltd · Bengaluru, Karnataka, India
Full-Time Entry STAPrimeTimeSDCOCVAOCV
Estimated market salary
₹12-20 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
3d ago
Category
Design
Experience
Entry
Country
India
Company Description
LeadIC Design Pvt Ltd accelerates semiconductor innovation through full-stack VLSI engineering expertise, supporting the complete chip development lifecycle for global semiconductor companies. Established in 2018, the company has grown into a trusted partner known for deep technical capability, strong execution ownership, and flexible engagement models.
With engineering teams across India and Canada, LeadIC delivers high-quality design services tailored for product-driven teams. Its capabilities span custom, memory and analog layout, analog and mixed-signal circuit design, digital design and RTL development, design verification, physical design, STA, DFT, physical verification, IP characterization, and FPGA-based prototyping.
LeadIC fosters an engineering culture built on ownership, quality-driven execution, and scalable offshore teams, forming long-term technical partnerships that help accelerate silicon success.
Role Description
This is a full-time STA (Static Timing Analysis) Engineer role based in Bengaluru, offered in a hybrid work model that combines onsite collaboration with flexibility for some work from home.
We are looking for professionals with 5+ years of relevant experience in Static Timing Analysis (STA).
The STA Engineer will perform block-level and full-chip timing analysis, including constraint development, timing closure, and signoff for complex digital and mixed-signal designs. Responsibilities include writing and validating SDC constraints, running STA across multiple corners and modes, analyzing timing reports, and driving fixes in collaboration with Physical Design and RTL teams.
The role also involves debugging timing violations, working on ECO implementation, supporting tape-out schedules, and maintaining timing methodologies and best practices. The STA Engineer will contribute to flow automation, documentation, and cross-functional reviews to ensure robust, silicon-ready designs.
Qualifications
Candidates should possess strong expertise in Static Timing Analysis, including SDC constraint development, timing closure, and signoff for multi-mode, multi-corner (MMMC) designs.
Candidates should possess hands-on experience with industry-standard STA and implementation tools such as PrimeTime, Tempus, Innovus, ICC2, Fusion Compiler, or equivalent.
Candidates should possess solid knowledge of digital design concepts, clocking, synchronous design, and RTL-to-GDSII flows.
Candidates should possess strong skills in analyzing setup/hold, recovery/removal, clock-domain crossings, on-chip variation, derates, and advanced-node timing challenges.
Candidates should possess experience working closely with Physical Design, RTL, and Verification teams to debug and resolve timing, functional, and integration issues.
Candidates should possess scripting and automation skills using Python, TCL, and/or Shell to improve STA flows, reporting, and engineering productivity.
Candidates should possess strong problem-solving abilities, attention to detail, and the capability to manage multiple blocks or projects under tight schedules.
Candidates should hold a Bachelor’s or Master’s degree in Electronics, Electrical Engineering, or a related discipline.
Experience: 5+ years
Location: Bengaluru
Work Model: Hybrid
Employment Type: Full-time
Interested candidates can reach out to me directly via LinkedIn DM or share their updated resume at nagu.ms@leadicdesign.com.
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LeadIC Design Pvt Ltd accelerates semiconductor innovation through full-stack VLSI engineering expertise, supporting the complete chip development lifecycle for global semiconductor companies. Established in 2018, the company has grown into a trusted partner known for deep technical capability, strong execution ownership, and flexible engagement models.
With engineering teams across India and Canada, LeadIC delivers high-quality design services tailored for product-driven teams. Its capabilities span custom, memory and analog layout, analog and mixed-signal circuit design, digital design and RTL development, design verification, physical design, STA, DFT, physical verification, IP characterization, and FPGA-based prototyping.
LeadIC fosters an engineering culture built on ownership, quality-driven execution, and scalable offshore teams, forming long-term technical partnerships that help accelerate silicon success.
Role Description
This is a full-time STA (Static Timing Analysis) Engineer role based in Bengaluru, offered in a hybrid work model that combines onsite collaboration with flexibility for some work from home.
We are looking for professionals with 5+ years of relevant experience in Static Timing Analysis (STA).
The STA Engineer will perform block-level and full-chip timing analysis, including constraint development, timing closure, and signoff for complex digital and mixed-signal designs. Responsibilities include writing and validating SDC constraints, running STA across multiple corners and modes, analyzing timing reports, and driving fixes in collaboration with Physical Design and RTL teams.
The role also involves debugging timing violations, working on ECO implementation, supporting tape-out schedules, and maintaining timing methodologies and best practices. The STA Engineer will contribute to flow automation, documentation, and cross-functional reviews to ensure robust, silicon-ready designs.
Qualifications
Candidates should possess strong expertise in Static Timing Analysis, including SDC constraint development, timing closure, and signoff for multi-mode, multi-corner (MMMC) designs.
Candidates should possess hands-on experience with industry-standard STA and implementation tools such as PrimeTime, Tempus, Innovus, ICC2, Fusion Compiler, or equivalent.
Candidates should possess solid knowledge of digital design concepts, clocking, synchronous design, and RTL-to-GDSII flows.
Candidates should possess strong skills in analyzing setup/hold, recovery/removal, clock-domain crossings, on-chip variation, derates, and advanced-node timing challenges.
Candidates should possess experience working closely with Physical Design, RTL, and Verification teams to debug and resolve timing, functional, and integration issues.
Candidates should possess scripting and automation skills using Python, TCL, and/or Shell to improve STA flows, reporting, and engineering productivity.
Candidates should possess strong problem-solving abilities, attention to detail, and the capability to manage multiple blocks or projects under tight schedules.
Candidates should hold a Bachelor’s or Master’s degree in Electronics, Electrical Engineering, or a related discipline.
Experience: 5+ years
Location: Bengaluru
Work Model: Hybrid
Employment Type: Full-time
Interested candidates can reach out to me directly via LinkedIn DM or share their updated resume at nagu.ms@leadicdesign.com.
Show more Show less