STA Engineer 5+ years

📢 Hiring: STA Engineer | 5+ Years Experience

We are looking for a skilled Static Timing Analysis (STA) Engineer with 5+ years of experience in VLSI design and timing signoff.

Qualification: BE/B.Tech

✅ Strong expertise in STA and Subsystem level
✅ Experience with PrimeTime and Timing Signoff flows
✅ Knowledge of SDC constraints, CDC, and low-power design concepts
✅ Ability to analyze and debug setup/hold violations
✅ Experience working with Physical Design and Design teams

Interested candidates kindly share below details & updated resume at javeriya_kewal@hcltech.com
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