STA and Synthesis Engineer

STA & Synthesis Lead Engineer
Experience: 5+ Years
Education: B.Tech/B.E./M.Tech/M.E. in VLSI, Electronics, Electrical Eng
Location: Bangalore
We are looking for an experienced STA & Synthesis Lead Engineer with hands-on experience in Logic synthesis, static timing analysis, timing closure, and design optimization. The ideal candidate will have strong expertise in PPA optimization, MMMC timing analysis, SDC constraints, ECO implementation, and formal equivalence checking, with the ability to work closely with RTL, DFT, and Physical Design teams.
The candidate will be responsible for driving synthesis and timing sign-off activities from RTL through implementation, identifying timing bottlenecks, and delivering optimized designs that meet Power, Performance, and Area (PPA) targets.
Key Responsibilities
1. Logic Synthesis & PPA Optimization
Perform physical-aware RTL-to-gate synthesis for complex digital designs.
Optimize synthesis results for Power, Performance, and Area (PPA) targets.
Analyze synthesis reports and identify opportunities for timing, area, and power improvements.
Work with RTL designers to resolve synthesis-related issues and improve RTL quality.
Support synthesis flows across block-level and top-level designs.
2. Constraint Development & Management
Develop, review, validate, and debug SDC timing constraints for block-level and top-level designs.
Define and maintain constraints for functional, scan, and DFT modes.
Handle clock definitions, generated clocks, clock relationships, I/O constraints, false paths, multicycle paths, and case analysis.
Debug constraint-related timing issues and ensure constraint completeness and correctness.
3. Static Timing Analysis & Sign-Off
Perform Static Timing Analysis (STA) across Multi-Corner Multi-Mode (MMMC) scenarios.
Drive timing sign-off for setup, hold, recovery, removal, and clock-gating checks.
Analyze critical paths, timing violations, clock interactions, and design bottlenecks.
Understand and account for clock skew, jitter, latency, uncertainty, and variation effects.
Perform timing analysis across functional and DFT/scan modes.
Support and debug CDC-related timing issues in collaboration with RTL/CDC teams.
4. Timing Closure & ECO
Identify critical timing paths and develop effective strategies for timing closure.
Generate, implement, and validate timing and functional ECOs.
Analyze the impact of ECOs on timing, area, power, and functionality.
Work closely with Physical Design/P&R teams to resolve post-placement and post-route timing issues.
Support iterative synthesis, implementation, and timing optimization until sign-off.
5. Formal Equivalence Checking
Perform formal equivalence checking between RTL and synthesized/optimized netlists.
Validate functional correctness following synthesis optimizations and ECO changes.
Debug equivalence failures and collaborate with RTL and design teams to resolve issues.
Ensure design changes maintain functional equivalence across implementation stages.
Technical Skills
5+ years of hands-on experience in synthesis and STA.
Deep understanding of timing concepts
Strong knowledge of MMMC timing analysis and sign-off methodologies.
Experience with SDC constraint development and debugging.
Good understanding of low-power design methodologies, including UPF/CPF.
Preferred Qualifications
Experience with advanced-node designs and complex SoC/block-level implementation.
Experience working with hierarchical and top-level STA.
Exposure to DFT/scan timing and test-mode constraints.
Experience with post-route timing analysis and sign-off.
Knowledge of clock-tree implementation and CTS-related timing issues.
Experience with timing ECOs and physical-aware optimization.
Strong debugging and problem-solving skills.
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